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Implement core resume operation. This is the last step of the sequencer resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP boot. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-12-joelagnelf@nvidia.com>
58 lines
1.4 KiB
Rust
58 lines
1.4 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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io::poll::read_poll_timeout,
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prelude::*,
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time::Delta, //
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};
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use crate::{
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driver::Bar0,
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falcon::{
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Falcon,
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FalconEngine,
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PFalcon2Base,
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PFalconBase, //
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},
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regs::{
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self,
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macros::RegisterBase, //
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},
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};
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/// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
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pub(crate) struct Gsp(());
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impl RegisterBase<PFalconBase> for Gsp {
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const BASE: usize = 0x00110000;
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}
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impl RegisterBase<PFalcon2Base> for Gsp {
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const BASE: usize = 0x00111000;
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}
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impl FalconEngine for Gsp {
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const ID: Self = Gsp(());
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}
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impl Falcon<Gsp> {
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/// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to
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/// allow GSP to signal CPU for processing new messages in message queue.
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pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) {
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regs::NV_PFALCON_FALCON_IRQSCLR::default()
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.set_swgen0(true)
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.write(bar, &Gsp::ID);
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}
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/// Checks if GSP reload/resume has completed during the boot process.
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pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> {
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read_poll_timeout(
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|| Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)),
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|val| val.boot_stage_3_handoff(),
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Delta::ZERO,
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timeout,
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)
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.map(|_| true)
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}
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}
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