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Some GPUs do not support using DMA to transfer code/data from system memory to Falcon memory, and instead must use programmed I/O (PIO). Add a function to the Falcon HAL to indicate whether a given GPU's Falcons support DMA for this purpose. Signed-off-by: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260122222848.2555890-10-ttabi@nvidia.com [acourbot@nvidia.com: add short code to call into the HAL.] [acourbot@nvidia.com: make `dma_load` private as per feedback.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
87 lines
2.7 KiB
Rust
87 lines
2.7 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::prelude::*;
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use crate::{
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driver::Bar0,
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falcon::{
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Falcon,
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FalconBromParams,
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FalconEngine, //
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},
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gpu::Chipset,
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};
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mod ga102;
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mod tu102;
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/// Method used to load data into falcon memory. Some GPU architectures need
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/// PIO and others can use DMA.
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pub(crate) enum LoadMethod {
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/// Programmed I/O
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Pio,
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/// Direct Memory Access
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Dma,
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}
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/// Hardware Abstraction Layer for Falcon cores.
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///
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/// Implements chipset-specific low-level operations. The trait is generic against [`FalconEngine`]
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/// so its `BASE` parameter can be used in order to avoid runtime bound checks when accessing
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/// registers.
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pub(crate) trait FalconHal<E: FalconEngine>: Send + Sync {
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/// Activates the Falcon core if the engine is a risvc/falcon dual engine.
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fn select_core(&self, _falcon: &Falcon<E>, _bar: &Bar0) -> Result {
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Ok(())
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}
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/// Returns the fused version of the signature to use in order to run a HS firmware on this
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/// falcon instance. `engine_id_mask` and `ucode_id` are obtained from the firmware header.
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fn signature_reg_fuse_version(
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&self,
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falcon: &Falcon<E>,
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bar: &Bar0,
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engine_id_mask: u16,
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ucode_id: u8,
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) -> Result<u32>;
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/// Program the boot ROM registers prior to starting a secure firmware.
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fn program_brom(&self, falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result;
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/// Check if the RISC-V core is active.
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/// Returns `true` if the RISC-V core is active, `false` otherwise.
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fn is_riscv_active(&self, bar: &Bar0) -> bool;
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/// Wait for memory scrubbing to complete.
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fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result;
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/// Reset the falcon engine.
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fn reset_eng(&self, bar: &Bar0) -> Result;
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/// returns the method needed to load data into Falcon memory
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fn load_method(&self) -> LoadMethod;
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}
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/// Returns a boxed falcon HAL adequate for `chipset`.
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///
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/// We use a heap-allocated trait object instead of a statically defined one because the
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/// generic `FalconEngine` argument makes it difficult to define all the combinations
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/// statically.
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pub(super) fn falcon_hal<E: FalconEngine + 'static>(
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chipset: Chipset,
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) -> Result<KBox<dyn FalconHal<E>>> {
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use Chipset::*;
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let hal = match chipset {
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TU102 | TU104 | TU106 | TU116 | TU117 => {
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KBox::new(tu102::Tu102::<E>::new(), GFP_KERNEL)? as KBox<dyn FalconHal<E>>
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}
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GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 => {
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KBox::new(ga102::Ga102::<E>::new(), GFP_KERNEL)? as KBox<dyn FalconHal<E>>
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}
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_ => return Err(ENOTSUPP),
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};
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Ok(hal)
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}
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