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Discover the hardware register layout for GEN3 devices through an RDMA virtual channel operation with the Control Plane (CP). Set up the corresponding hardware attributes specific to GEN3 devices. Signed-off-by: Christopher Bednarz <christopher.n.bednarz@intel.com> Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com> Link: https://patch.msgid.link/20250827152545.2056-4-tatyana.e.nikolova@intel.com Tested-by: Jacob Moroni <jmoroni@google.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
74 lines
2.6 KiB
C
74 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2017 - 2021 Intel Corporation */
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#ifndef ICRDMA_HW_H
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#define ICRDMA_HW_H
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#include "irdma.h"
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#define VFPE_CQPTAIL1 0x0000a000
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#define VFPE_CQPDB1 0x0000bc00
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#define VFPE_CCQPSTATUS1 0x0000b800
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#define VFPE_CCQPHIGH1 0x00009800
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#define VFPE_CCQPLOW1 0x0000ac00
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#define VFPE_CQARM1 0x0000b400
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#define VFPE_CQARM1 0x0000b400
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#define VFPE_CQACK1 0x0000b000
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#define VFPE_AEQALLOC1 0x0000a400
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#define VFPE_CQPERRCODES1 0x00009c00
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#define VFPE_WQEALLOC1 0x0000c000
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#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */
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#define PFPE_CQPTAIL 0x00500880
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#define PFPE_CQPDB 0x00500800
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#define PFPE_CCQPSTATUS 0x0050a000
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#define PFPE_CCQPHIGH 0x0050a100
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#define PFPE_CCQPLOW 0x0050a080
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#define PFPE_CQARM 0x00502c00
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#define PFPE_CQACK 0x00502c80
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#define PFPE_AEQALLOC 0x00502d00
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#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */
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#define GLPCI_LBARCTRL 0x0009de74
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#define GLPE_CPUSTATUS0 0x0050ba5c
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#define GLPE_CPUSTATUS1 0x0050ba60
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#define GLPE_CPUSTATUS2 0x0050ba64
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#define PFINT_AEQCTL 0x0016cb00
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#define PFPE_CQPERRCODES 0x0050a200
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#define PFPE_WQEALLOC 0x00504400
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#define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */
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#define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */
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#define PFHMC_PDINV 0x00520300
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#define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */
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#define GLPE_CRITERR 0x00534000
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#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
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#define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024)
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#define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024)
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/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
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#define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0
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#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
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#define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31
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#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
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#define ICRDMA_CQPSQ_STAG_PDID_S 46
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#define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
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#define ICRDMA_CQPSQ_CQ_CEQID_S 22
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#define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
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#define ICRDMA_CQPSQ_CQ_CQID_S 0
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#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
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#define ICRDMA_COMMIT_FPM_CQCNT_S 0
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#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
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#define ICRDMA_CQPSQ_UPESD_HMCFNID_S 0
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#define ICRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
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enum icrdma_device_caps_const {
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ICRDMA_MAX_STATS_COUNT = 128,
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ICRDMA_MAX_IRD_SIZE = 127,
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ICRDMA_MAX_ORD_SIZE = 255,
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ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */,
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ICRDMA_MAX_PUSH_PAGE_COUNT = 256,
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};
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void icrdma_init_hw(struct irdma_sc_dev *dev);
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#endif /* ICRDMA_HW_H*/
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