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Discover the hardware register layout for GEN3 devices through an RDMA virtual channel operation with the Control Plane (CP). Set up the corresponding hardware attributes specific to GEN3 devices. Signed-off-by: Christopher Bednarz <christopher.n.bednarz@intel.com> Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com> Link: https://patch.msgid.link/20250827152545.2056-4-tatyana.e.nikolova@intel.com Tested-by: Jacob Moroni <jmoroni@google.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
33 lines
924 B
C
33 lines
924 B
C
/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
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/* Copyright (c) 2021 - 2024 Intel Corporation */
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#ifndef IG3RDMA_HW_H
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#define IG3RDMA_HW_H
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#define IG3_MAX_APFS 1
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#define IG3_MAX_AVFS 0
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#define IG3_PF_RDMA_REGION_OFFSET 0xBC00000
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#define IG3_PF_RDMA_REGION_LEN 0x401000
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#define IG3_VF_RDMA_REGION_OFFSET 0x8C00
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#define IG3_VF_RDMA_REGION_LEN 0x8400
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enum ig3rdma_device_caps_const {
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IG3RDMA_MAX_WQ_FRAGMENT_COUNT = 14,
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IG3RDMA_MAX_SGE_RD = 14,
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IG3RDMA_MAX_STATS_COUNT = 128,
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IG3RDMA_MAX_IRD_SIZE = 64,
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IG3RDMA_MAX_ORD_SIZE = 64,
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IG3RDMA_MIN_WQ_SIZE = 16 /* WQEs */,
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IG3RDMA_MAX_INLINE_DATA_SIZE = 216,
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IG3RDMA_MAX_PF_PUSH_PAGE_COUNT = 8192,
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IG3RDMA_MAX_VF_PUSH_PAGE_COUNT = 16,
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};
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void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset);
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int ig3rdma_vchnl_send_sync(struct irdma_sc_dev *dev, u8 *msg, u16 len,
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u8 *recv_msg, u16 *recv_len);
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#endif /* IG3RDMA_HW_H*/
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