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vpu4 depends on more than one clock source. Thus far hardware versions up to vpu3x have been clocked by a single source. This adds support for multiple clocks by, - Adding a lookup table - Configuring OPP table for video device with different video clocks - Setting OPP for multiple clocks during dev_pm_opp_set_opp() This patch extends the support for multiple clocks in driver, which would be used in subsequent patch for kaanapali, when the platform data is prepared. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Co-developed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
141 lines
3.1 KiB
C
141 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <media/v4l2-mem2mem.h>
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#include "iris_buffer.h"
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#include "iris_instance.h"
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#include "iris_power.h"
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#include "iris_resources.h"
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#include "iris_vpu_common.h"
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static u32 iris_calc_bw(struct iris_inst *inst, struct icc_vote_data *data)
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{
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const struct bw_info *bw_tbl = NULL;
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struct iris_core *core = inst->core;
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u32 num_rows, i, mbs, mbps;
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u32 icc_bw = 0;
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mbs = DIV_ROUND_UP(data->height, 16) * DIV_ROUND_UP(data->width, 16);
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mbps = mbs * data->fps;
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if (mbps == 0)
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goto exit;
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bw_tbl = core->iris_platform_data->bw_tbl_dec;
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num_rows = core->iris_platform_data->bw_tbl_dec_size;
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for (i = 0; i < num_rows; i++) {
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if (i != 0 && mbps > bw_tbl[i].mbs_per_sec)
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break;
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icc_bw = bw_tbl[i].bw_ddr;
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}
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exit:
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return icc_bw;
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}
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static int iris_set_interconnects(struct iris_inst *inst)
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{
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struct iris_core *core = inst->core;
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struct iris_inst *instance;
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u64 total_bw_ddr = 0;
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int ret;
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mutex_lock(&core->lock);
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list_for_each_entry(instance, &core->instances, list) {
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if (!instance->max_input_data_size)
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continue;
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total_bw_ddr += instance->power.icc_bw;
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}
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ret = iris_set_icc_bw(core, total_bw_ddr);
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mutex_unlock(&core->lock);
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return ret;
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}
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static int iris_vote_interconnects(struct iris_inst *inst)
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{
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struct icc_vote_data *vote_data = &inst->icc_data;
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struct v4l2_format *inp_f = inst->fmt_src;
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vote_data->width = inp_f->fmt.pix_mp.width;
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vote_data->height = inp_f->fmt.pix_mp.height;
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vote_data->fps = DEFAULT_FPS;
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inst->power.icc_bw = iris_calc_bw(inst, vote_data);
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return iris_set_interconnects(inst);
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}
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static int iris_set_clocks(struct iris_inst *inst)
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{
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struct iris_core *core = inst->core;
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struct iris_inst *instance;
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u64 freq = 0;
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int ret;
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mutex_lock(&core->lock);
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list_for_each_entry(instance, &core->instances, list) {
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if (!instance->max_input_data_size)
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continue;
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freq += instance->power.min_freq;
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}
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core->power.clk_freq = freq;
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ret = iris_opp_set_rate(core->dev, freq);
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mutex_unlock(&core->lock);
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return ret;
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}
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static int iris_scale_clocks(struct iris_inst *inst)
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{
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const struct vpu_ops *vpu_ops = inst->core->iris_platform_data->vpu_ops;
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struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
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struct v4l2_m2m_buffer *buffer, *n;
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struct iris_buffer *buf;
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size_t data_size = 0;
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v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buffer, n) {
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buf = to_iris_buffer(&buffer->vb);
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data_size = max(data_size, buf->data_size);
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}
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inst->max_input_data_size = data_size;
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if (!inst->max_input_data_size)
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return 0;
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inst->power.min_freq = vpu_ops->calc_freq(inst, inst->max_input_data_size);
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return iris_set_clocks(inst);
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}
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int iris_scale_power(struct iris_inst *inst)
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{
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struct iris_core *core = inst->core;
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int ret;
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if (pm_runtime_suspended(core->dev)) {
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ret = pm_runtime_resume_and_get(core->dev);
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if (ret < 0)
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return ret;
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pm_runtime_put_autosuspend(core->dev);
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}
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ret = iris_scale_clocks(inst);
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if (ret)
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return ret;
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return iris_vote_interconnects(inst);
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}
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