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23794bec1c
Add very basic DSA driver for MaxLinear's MxL862xx switches. In contrast to previous MaxLinear switches the MxL862xx has a built-in processor that runs a sophisticated firmware based on Zephyr RTOS. Interaction between the host and the switch hence is organized using a software API of that firmware rather than accessing hardware registers directly. Add descriptions of the most basic firmware API calls to access the built-in MDIO bus hosting the 2.5GE PHYs, basic port control as well as setting up the CPU port. Implement a very basic DSA driver using that API which is sufficient to get packets flowing between the user ports and the CPU port. The firmware offers all features one would expect from a modern switch hardware, they are going to be added one by one in follow-up patch series. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://patch.msgid.link/ccde07e8cf33d8ae243000013b57cfaa2695e0a9.1770433307.git.daniel@makrotopia.org Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __MXL862XX_CMD_H
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#define __MXL862XX_CMD_H
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#define MXL862XX_MMD_DEV 30
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#define MXL862XX_MMD_REG_CTRL 0
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#define MXL862XX_MMD_REG_LEN_RET 1
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#define MXL862XX_MMD_REG_DATA_FIRST 2
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#define MXL862XX_MMD_REG_DATA_LAST 95
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#define MXL862XX_MMD_REG_DATA_MAX_SIZE \
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(MXL862XX_MMD_REG_DATA_LAST - MXL862XX_MMD_REG_DATA_FIRST + 1)
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#define MXL862XX_COMMON_MAGIC 0x100
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#define MXL862XX_BRDG_MAGIC 0x300
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#define MXL862XX_BRDGPORT_MAGIC 0x400
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#define MXL862XX_CTP_MAGIC 0x500
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#define MXL862XX_SWMAC_MAGIC 0xa00
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#define MXL862XX_SS_MAGIC 0x1600
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#define GPY_GPY2XX_MAGIC 0x1800
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#define SYS_MISC_MAGIC 0x1900
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#define MXL862XX_COMMON_CFGGET (MXL862XX_COMMON_MAGIC + 0x9)
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#define MXL862XX_COMMON_REGISTERMOD (MXL862XX_COMMON_MAGIC + 0x11)
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#define MXL862XX_BRIDGE_ALLOC (MXL862XX_BRDG_MAGIC + 0x1)
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#define MXL862XX_BRIDGE_CONFIGSET (MXL862XX_BRDG_MAGIC + 0x2)
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#define MXL862XX_BRIDGE_CONFIGGET (MXL862XX_BRDG_MAGIC + 0x3)
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#define MXL862XX_BRIDGE_FREE (MXL862XX_BRDG_MAGIC + 0x4)
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#define MXL862XX_BRIDGEPORT_ALLOC (MXL862XX_BRDGPORT_MAGIC + 0x1)
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#define MXL862XX_BRIDGEPORT_CONFIGSET (MXL862XX_BRDGPORT_MAGIC + 0x2)
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#define MXL862XX_BRIDGEPORT_CONFIGGET (MXL862XX_BRDGPORT_MAGIC + 0x3)
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#define MXL862XX_BRIDGEPORT_FREE (MXL862XX_BRDGPORT_MAGIC + 0x4)
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#define MXL862XX_CTP_PORTASSIGNMENTSET (MXL862XX_CTP_MAGIC + 0x3)
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#define MXL862XX_MAC_TABLECLEARCOND (MXL862XX_SWMAC_MAGIC + 0x8)
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#define MXL862XX_SS_SPTAG_SET (MXL862XX_SS_MAGIC + 0x02)
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#define INT_GPHY_READ (GPY_GPY2XX_MAGIC + 0x01)
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#define INT_GPHY_WRITE (GPY_GPY2XX_MAGIC + 0x02)
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#define SYS_MISC_FW_VERSION (SYS_MISC_MAGIC + 0x02)
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#define MMD_API_MAXIMUM_ID 0x7fff
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#endif /* __MXL862XX_CMD_H */
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