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The "usxgmii" phy-mode that the Felix switch ports support on LS1028A is not quite USXGMII, it is defined by the USXGMII multiport specification document as 10G-QXGMII. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. This change is needed in preparation for the lynx-10g SerDes driver on LS1028A, which will make a more clear distinction between usxgmii (supported on lane 0) and 10g-qxgmii (supported on lane 1). These protocols have their configuration in different PCCR registers (PCCRB vs PCCR9). Continue parsing and supporting single-port-per-lane USXGMII when found in the device tree as usual (because it works), but add support for 10G-QXGMII too. Using phy-mode = "10g-qxgmii" will be required when modifying the device trees to specify a "phys" phandle to the SerDes lane. The result when the "phys" phandle is present but the phy-mode is wrong is undefined. The only PHY driver in known use with this phy-mode, AQR412C, will gain logic to transition from "usxgmii" to "10g-qxgmii" in a future change. Prepare the driver by also setting PHY_INTERFACE_MODE_10G_QXGMII in supported_interfaces when PHY_INTERFACE_MODE_USXGMII is there, to prevent breakage with existing device trees. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20250903130730.2836022-3-vladimir.oltean@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
110 lines
3.9 KiB
C
110 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2019 NXP
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*/
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#ifndef _MSCC_FELIX_H
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#define _MSCC_FELIX_H
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#define ocelot_to_felix(o) container_of((o), struct felix, ocelot)
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#define FELIX_MAC_QUIRKS OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION
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#define OCELOT_PORT_MODE_NONE 0
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#define OCELOT_PORT_MODE_INTERNAL BIT(0)
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#define OCELOT_PORT_MODE_SGMII BIT(1)
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#define OCELOT_PORT_MODE_QSGMII BIT(2)
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#define OCELOT_PORT_MODE_2500BASEX BIT(3)
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#define OCELOT_PORT_MODE_USXGMII BIT(4) /* compatibility */
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#define OCELOT_PORT_MODE_1000BASEX BIT(5)
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#define OCELOT_PORT_MODE_10G_QXGMII BIT(6)
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struct device_node;
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/* Platform-specific information */
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struct felix_info {
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/* Hardcoded resources provided by the hardware instantiation. */
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const struct resource *resources;
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size_t num_resources;
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/* Names of the mandatory resources that will be requested during
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* probe. Must have TARGET_MAX elements, since it is indexed by target.
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*/
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const char *const *resource_names;
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const struct reg_field *regfields;
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const u32 *const *map;
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const struct ocelot_ops *ops;
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const u32 *port_modes;
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int num_mact_rows;
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int num_ports;
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struct vcap_props *vcap;
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u16 vcap_pol_base;
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u16 vcap_pol_max;
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u16 vcap_pol_base2;
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u16 vcap_pol_max2;
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const struct ptp_clock_info *ptp_caps;
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unsigned long quirks;
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/* Some Ocelot switches are integrated into the SoC without the
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* extraction IRQ line connected to the ARM GIC. By enabling this
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* workaround, the few packets that are delivered to the CPU port
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* module (currently only PTP) are copied not only to the hardware CPU
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* port module, but also to the 802.1Q Ethernet CPU port, and polling
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* the extraction registers is triggered once the DSA tagger sees a PTP
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* frame. The Ethernet frame is only used as a notification: it is
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* dropped, and the original frame is extracted over MMIO and annotated
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* with the RX timestamp.
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*/
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bool quirk_no_xtr_irq;
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int (*mdio_bus_alloc)(struct ocelot *ocelot);
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void (*mdio_bus_free)(struct ocelot *ocelot);
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int (*port_setup_tc)(struct dsa_switch *ds, int port,
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enum tc_setup_type type, void *type_data);
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void (*port_sched_speed_set)(struct ocelot *ocelot, int port,
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u32 speed);
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void (*phylink_mac_config)(struct ocelot *ocelot, int port,
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unsigned int mode,
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const struct phylink_link_state *state);
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int (*configure_serdes)(struct ocelot *ocelot, int port,
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struct device_node *portnp);
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int (*request_irq)(struct ocelot *ocelot);
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};
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/* Methods for initializing the hardware resources specific to a tagging
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* protocol (like the NPI port, for "ocelot" or "seville", or the VCAP TCAMs,
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* for "ocelot-8021q").
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* It is important that the resources configured here do not have side effects
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* for the other tagging protocols. If that is the case, their configuration
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* needs to go to felix_tag_proto_setup_shared().
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*/
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struct felix_tag_proto_ops {
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int (*setup)(struct dsa_switch *ds);
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void (*teardown)(struct dsa_switch *ds);
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unsigned long (*get_host_fwd_mask)(struct dsa_switch *ds);
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int (*change_conduit)(struct dsa_switch *ds, int port,
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struct net_device *conduit,
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struct netlink_ext_ack *extack);
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};
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/* DSA glue / front-end for struct ocelot */
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struct felix {
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struct dsa_switch *ds;
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const struct felix_info *info;
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struct ocelot ocelot;
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struct mii_bus *imdio;
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struct phylink_pcs **pcs;
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resource_size_t switch_base;
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enum dsa_tag_protocol tag_proto;
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const struct felix_tag_proto_ops *tag_proto_ops;
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struct kthread_worker *xmit_worker;
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unsigned long host_flood_uc_mask;
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unsigned long host_flood_mc_mask;
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};
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int felix_register_switch(struct device *dev, resource_size_t switch_base,
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int num_flooding_pgids, bool ptp,
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bool mm_supported,
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enum dsa_tag_protocol init_tag_proto,
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const struct felix_info *info);
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struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port);
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int felix_netdev_to_port(struct net_device *dev);
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#endif
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