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a6bac18229
Use int instead of unsigned int for the 'ret' variable to store return values from functions that either return zero on success or negative error codes on failure. Storing negative error codes in an unsigned int causes no runtime issues, but it's ugly as pants, Change 'ret' from unsigned int to int type - this change has no runtime impact. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://patch.msgid.link/20250826142159.525059-1-rongqianfeng@vivo.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
406 lines
9.3 KiB
C
406 lines
9.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
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* Copyright (c) 2014, Synopsys, Inc.
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* All rights reserved
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/kmod.h>
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#include <linux/delay.h>
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include "xgbe.h"
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#include "xgbe-common.h"
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#define XGBE_ABORT_COUNT 500
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#define XGBE_DISABLE_COUNT 1000
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#define XGBE_STD_SPEED 1
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#define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
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#define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
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#define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
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#define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
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#define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \
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XGBE_INTR_TX_EMPTY | \
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XGBE_INTR_TX_ABRT | \
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XGBE_INTR_STOP_DET)
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#define XGBE_I2C_READ BIT(8)
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#define XGBE_I2C_STOP BIT(9)
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static int xgbe_i2c_abort(struct xgbe_prv_data *pdata)
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{
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unsigned int wait = XGBE_ABORT_COUNT;
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/* Must be enabled to recognize the abort request */
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
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/* Issue the abort */
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
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while (wait--) {
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if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
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return 0;
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usleep_range(500, 600);
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}
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return -EBUSY;
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}
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static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
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{
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unsigned int wait = XGBE_DISABLE_COUNT;
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unsigned int mode = enable ? 1 : 0;
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while (wait--) {
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XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
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if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
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return 0;
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usleep_range(100, 110);
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}
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return -EBUSY;
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}
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static int xgbe_i2c_disable(struct xgbe_prv_data *pdata)
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{
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int ret;
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ret = xgbe_i2c_set_enable(pdata, false);
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if (ret) {
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/* Disable failed, try an abort */
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ret = xgbe_i2c_abort(pdata);
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if (ret)
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return ret;
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/* Abort succeeded, try to disable again */
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ret = xgbe_i2c_set_enable(pdata, false);
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}
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return ret;
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}
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static int xgbe_i2c_enable(struct xgbe_prv_data *pdata)
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{
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return xgbe_i2c_set_enable(pdata, true);
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}
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static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
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{
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XI2C_IOREAD(pdata, IC_CLR_INTR);
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}
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static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
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{
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XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
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}
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static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
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{
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XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
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}
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static void xgbe_i2c_write(struct xgbe_prv_data *pdata)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int tx_slots;
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unsigned int cmd;
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/* Configured to never receive Rx overflows, so fill up Tx fifo */
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tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
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while (tx_slots && state->tx_len) {
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if (state->op->cmd == XGBE_I2C_CMD_READ)
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cmd = XGBE_I2C_READ;
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else
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cmd = *state->tx_buf++;
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if (state->tx_len == 1)
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XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
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XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
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tx_slots--;
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state->tx_len--;
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}
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/* No more Tx operations, so ignore TX_EMPTY and return */
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if (!state->tx_len)
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XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
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}
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static void xgbe_i2c_read(struct xgbe_prv_data *pdata)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int rx_slots;
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/* Anything to be read? */
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if (state->op->cmd != XGBE_I2C_CMD_READ)
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return;
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rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
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while (rx_slots && state->rx_len) {
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*state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
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state->rx_len--;
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rx_slots--;
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}
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}
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static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata,
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unsigned int isr)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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if (isr & XGBE_INTR_TX_ABRT) {
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state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
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XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
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}
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if (isr & XGBE_INTR_STOP_DET)
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XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
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}
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static void xgbe_i2c_isr_bh_work(struct work_struct *work)
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{
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struct xgbe_prv_data *pdata = from_work(pdata, work, i2c_bh_work);
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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unsigned int isr;
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isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
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if (!isr)
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goto reissue_check;
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netif_dbg(pdata, intr, pdata->netdev,
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"I2C interrupt received: status=%#010x\n", isr);
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xgbe_i2c_clear_isr_interrupts(pdata, isr);
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if (isr & XGBE_INTR_TX_ABRT) {
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netif_dbg(pdata, link, pdata->netdev,
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"I2C TX_ABRT received (%#010x) for target %#04x\n",
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state->tx_abort_source, state->op->target);
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xgbe_i2c_disable_interrupts(pdata);
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state->ret = -EIO;
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goto out;
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}
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/* Check for data in the Rx fifo */
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xgbe_i2c_read(pdata);
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/* Fill up the Tx fifo next */
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xgbe_i2c_write(pdata);
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out:
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/* Complete on an error or STOP condition */
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if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
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complete(&pdata->i2c_complete);
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reissue_check:
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/* Reissue interrupt if status is not clear */
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if (pdata->vdata->irq_reissue_support)
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XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2);
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}
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static irqreturn_t xgbe_i2c_isr(int irq, void *data)
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{
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struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
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if (pdata->isr_as_bh_work)
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queue_work(system_bh_wq, &pdata->i2c_bh_work);
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else
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xgbe_i2c_isr_bh_work(&pdata->i2c_bh_work);
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return IRQ_HANDLED;
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}
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static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
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{
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unsigned int reg;
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reg = XI2C_IOREAD(pdata, IC_CON);
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XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
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XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
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XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
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XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
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XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
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XI2C_IOWRITE(pdata, IC_CON, reg);
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}
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static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
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{
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struct xgbe_i2c *i2c = &pdata->i2c;
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unsigned int reg;
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reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
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i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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MAX_SPEED_MODE);
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i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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RX_BUFFER_DEPTH);
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i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
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TX_BUFFER_DEPTH);
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if (netif_msg_probe(pdata))
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dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n",
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"MAX_SPEED_MODE", i2c->max_speed_mode,
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"RX_BUFFER_DEPTH", i2c->rx_fifo_size,
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"TX_BUFFER_DEPTH", i2c->tx_fifo_size);
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}
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static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
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{
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XI2C_IOWRITE(pdata, IC_TAR, addr);
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}
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static irqreturn_t xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata)
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{
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xgbe_i2c_isr_bh_work(&pdata->i2c_bh_work);
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return IRQ_HANDLED;
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}
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static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
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{
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struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
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int ret;
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mutex_lock(&pdata->i2c_mutex);
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reinit_completion(&pdata->i2c_complete);
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ret = xgbe_i2c_disable(pdata);
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if (ret) {
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netdev_err(pdata->netdev, "failed to disable i2c master\n");
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goto unlock;
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}
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xgbe_i2c_set_target(pdata, op->target);
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memset(state, 0, sizeof(*state));
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state->op = op;
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state->tx_len = op->len;
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state->tx_buf = op->buf;
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state->rx_len = op->len;
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state->rx_buf = op->buf;
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xgbe_i2c_clear_all_interrupts(pdata);
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ret = xgbe_i2c_enable(pdata);
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if (ret) {
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netdev_err(pdata->netdev, "failed to enable i2c master\n");
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goto unlock;
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}
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/* Enabling the interrupts will cause the TX FIFO empty interrupt to
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* fire and begin to process the command via the ISR.
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*/
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xgbe_i2c_enable_interrupts(pdata);
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if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) {
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netdev_err(pdata->netdev, "i2c operation timed out\n");
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ret = -ETIMEDOUT;
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goto disable;
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}
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ret = state->ret;
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if (ret) {
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if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
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ret = -ENOTCONN;
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else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
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ret = -EAGAIN;
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}
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disable:
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xgbe_i2c_disable_interrupts(pdata);
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xgbe_i2c_disable(pdata);
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unlock:
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mutex_unlock(&pdata->i2c_mutex);
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return ret;
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}
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static void xgbe_i2c_stop(struct xgbe_prv_data *pdata)
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{
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if (!pdata->i2c.started)
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return;
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netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n");
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pdata->i2c.started = 0;
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xgbe_i2c_disable_interrupts(pdata);
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xgbe_i2c_disable(pdata);
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xgbe_i2c_clear_all_interrupts(pdata);
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if (pdata->dev_irq != pdata->i2c_irq) {
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devm_free_irq(pdata->dev, pdata->i2c_irq, pdata);
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cancel_work_sync(&pdata->i2c_bh_work);
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}
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}
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static int xgbe_i2c_start(struct xgbe_prv_data *pdata)
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{
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int ret;
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if (pdata->i2c.started)
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return 0;
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netif_dbg(pdata, link, pdata->netdev, "starting I2C\n");
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/* If we have a separate I2C irq, enable it */
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if (pdata->dev_irq != pdata->i2c_irq) {
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INIT_WORK(&pdata->i2c_bh_work, xgbe_i2c_isr_bh_work);
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ret = devm_request_irq(pdata->dev, pdata->i2c_irq,
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xgbe_i2c_isr, 0, pdata->i2c_name,
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pdata);
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if (ret) {
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netdev_err(pdata->netdev, "i2c irq request failed\n");
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return ret;
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}
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}
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pdata->i2c.started = 1;
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return 0;
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}
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static int xgbe_i2c_init(struct xgbe_prv_data *pdata)
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{
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int ret;
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xgbe_i2c_disable_interrupts(pdata);
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ret = xgbe_i2c_disable(pdata);
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if (ret) {
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dev_err(pdata->dev, "failed to disable i2c master\n");
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return ret;
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}
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xgbe_i2c_get_features(pdata);
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xgbe_i2c_set_mode(pdata);
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xgbe_i2c_clear_all_interrupts(pdata);
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return 0;
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}
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void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
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{
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i2c_if->i2c_init = xgbe_i2c_init;
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i2c_if->i2c_start = xgbe_i2c_start;
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i2c_if->i2c_stop = xgbe_i2c_stop;
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i2c_if->i2c_xfer = xgbe_i2c_xfer;
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i2c_if->i2c_isr = xgbe_i2c_combined_isr;
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}
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