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670d10509f
Remove many xxx_SHIFT definitions for descriptors, isntead using FIELD_PREP(), FIELD_GET(), and u32_replace_bits() as appropriate to manipulate the bitfields. This avoids potential errors where an incorrect shift is used with a mask. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vdtw2-00000002Gto-3ZPt@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*******************************************************************************
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Header File to describe Normal/enhanced descriptor functions used for RING
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and CHAINED modes.
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Copyright(C) 2011 STMicroelectronics Ltd
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It defines all the functions used to handle the normal/enhanced
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descriptors in case of the DMA is configured to work in chained or
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in ring mode.
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#ifndef __DESC_COM_H__
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#define __DESC_COM_H__
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/* Specific functions used for Ring mode */
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/* Enhanced descriptors */
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static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end,
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int bfsize)
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{
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if (bfsize == BUF_SIZE_16KiB)
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p->des1 |= cpu_to_le32(FIELD_PREP(ERDES1_BUFFER2_SIZE_MASK,
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BUF_SIZE_8KiB));
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if (end)
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p->des1 |= cpu_to_le32(ERDES1_END_RING);
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}
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static inline void enh_desc_end_tx_desc_on_ring(struct dma_desc *p, int end)
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{
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if (end)
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p->des0 |= cpu_to_le32(ETDES0_END_RING);
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else
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p->des0 &= cpu_to_le32(~ETDES0_END_RING);
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}
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/* The maximum buffer 1 size is 8KiB - 1. However, we limit to 4KiB. */
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static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
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{
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unsigned int buffer1_max_length = BUF_SIZE_4KiB;
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if (unlikely(len > buffer1_max_length)) {
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p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER2_SIZE_MASK,
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len - buffer1_max_length) |
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FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,
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buffer1_max_length));
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} else {
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p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,
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len));
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}
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}
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/* Normal descriptors */
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static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize)
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{
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if (bfsize >= BUF_SIZE_2KiB) {
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int bfsize2;
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bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1);
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p->des1 |= cpu_to_le32(FIELD_PREP(RDES1_BUFFER2_SIZE_MASK,
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bfsize2));
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}
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if (end)
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p->des1 |= cpu_to_le32(RDES1_END_RING);
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}
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static inline void ndesc_end_tx_desc_on_ring(struct dma_desc *p, int end)
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{
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if (end)
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p->des1 |= cpu_to_le32(TDES1_END_RING);
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else
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p->des1 &= cpu_to_le32(~TDES1_END_RING);
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}
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/* The maximum buffer 1 size is 2KiB - 1, limited by the mask width */
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static inline void norm_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
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{
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unsigned int buffer1_max_length = BUF_SIZE_2KiB - 1;
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if (unlikely(len > buffer1_max_length)) {
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p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER2_SIZE_MASK,
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len - buffer1_max_length) |
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FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,
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buffer1_max_length));
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} else {
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p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,
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len));
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}
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}
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/* Specific functions used for Chain mode */
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/* Enhanced descriptors */
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static inline void ehn_desc_rx_set_on_chain(struct dma_desc *p)
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{
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p->des1 |= cpu_to_le32(ERDES1_SECOND_ADDRESS_CHAINED);
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}
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static inline void enh_desc_end_tx_desc_on_chain(struct dma_desc *p)
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{
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p->des0 |= cpu_to_le32(ETDES0_SECOND_ADDRESS_CHAINED);
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}
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static inline void enh_set_tx_desc_len_on_chain(struct dma_desc *p, int len)
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{
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p->des1 |= cpu_to_le32(len & ETDES1_BUFFER1_SIZE_MASK);
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}
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/* Normal descriptors */
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static inline void ndesc_rx_set_on_chain(struct dma_desc *p, int end)
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{
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p->des1 |= cpu_to_le32(RDES1_SECOND_ADDRESS_CHAINED);
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}
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static inline void ndesc_tx_set_on_chain(struct dma_desc *p)
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{
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p->des1 |= cpu_to_le32(TDES1_SECOND_ADDRESS_CHAINED);
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}
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static inline void norm_set_tx_desc_len_on_chain(struct dma_desc *p, int len)
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{
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p->des1 |= cpu_to_le32(len & TDES1_BUFFER1_SIZE_MASK);
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}
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#endif /* __DESC_COM_H__ */
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