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Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks
compared to 1 clock on other SoCs.
Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clocks, as
listed in section 4.4.4.1 ("Block Diagram of the Clock System"), module
clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
Reset definitions referring to registers CPG_RST_* in Section 4.4.3
("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324114329.268249-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
120 lines
3.4 KiB
YAML
120 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
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Standby Mode share the same register block. On RZ/V2M, the functionality is
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similar, but does not have Clock Monitor Registers.
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They provide the following functionalities:
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- The CPG block generates various core clocks,
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- The Module Standby Mode block provides two functions:
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1. Module Standby, providing a Clock Domain to control the clock supply
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to individual SoC devices,
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2. Reset Control, to perform a software reset of individual SoC devices.
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properties:
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compatible:
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enum:
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- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
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- renesas,r9a07g044-cpg # RZ/G2{L,LC}
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- renesas,r9a07g054-cpg # RZ/V2L
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- renesas,r9a08g045-cpg # RZ/G3S
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- renesas,r9a08g046-cpg # RZ/G3L
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- renesas,r9a09g011-cpg # RZ/V2M
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: Clock source to CPG can be either from external clock
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input (EXCLK) or crystal oscillator (XIN/XOUT).
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- description: ETH0 TXC clock input
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- description: ETH0 RXC clock input
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- description: ETH1 TXC clock input
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- description: ETH1 RXC clock input
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clock-names:
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minItems: 1
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items:
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- const: extal
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- const: eth0_txc_tx_clk
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- const: eth0_rxc_rx_clk
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- const: eth1_txc_tx_clk
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- const: eth1_rxc_rx_clk
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/r9a0*-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
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const: 2
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'#power-domain-cells':
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description:
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SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
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can be power-managed through Module Standby should refer to the CPG device
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node in their "power-domains" property, as documented by the generic PM
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Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the reset number, as defined in
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<dt-bindings/clock/r9a0*-cpg.h>.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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- '#reset-cells'
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g046-cpg
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then:
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properties:
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clocks:
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minItems: 5
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clock-names:
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minItems: 5
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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additionalProperties: false
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examples:
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- |
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a07g044-cpg";
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reg = <0x11010000 0x10000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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