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The six PCIe controllers found on Tegra264 are of two types: one is used for the internal GPU and therefore is not connected to a UPHY and the remaining five controllers are typically routed to a PCI slot and have additional controls for the physical link. While these controllers can be switched into endpoint mode, this binding describes the root complex mode only. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
150 lines
4.4 KiB
YAML
150 lines
4.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra264 PCIe controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra264-pcie
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reg:
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description: |
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Of the six PCIe controllers found on Tegra264, one (C0) is used for the
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internal GPU and the other five (C1-C5) are routed to connectors such as
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PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
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through C5, but not for C0.
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minItems: 4
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items:
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- description: ECAM-compatible configuration space
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- description: application layer registers
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- description: transaction layer registers
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- description: privileged transaction layer registers
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- description: data link/physical layer registers (not available on C0)
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reg-names:
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minItems: 4
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items:
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- const: ecam
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- const: xal
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- const: xtl
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- const: xtl-pri
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- const: xpl
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interrupts:
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minItems: 1
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maxItems: 4
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dma-coherent: true
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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Must contain a pair of phandle (to the BPMP controller node) and
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controller ID. The following are the controller IDs for each controller:
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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items:
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- items:
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- description: phandle to the BPMP controller node
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- description: PCIe controller ID
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maximum: 5
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required:
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- interrupt-map
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- interrupt-map-mask
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- iommu-map
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- msi-map
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- nvidia,bpmp
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pci@c000000 {
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compatible = "nvidia,tegra264-pcie";
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reg = <0xd0 0xb0000000 0x0 0x10000000>,
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<0x00 0x0c000000 0x0 0x00004000>,
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<0x00 0x0c004000 0x0 0x00001000>,
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<0x00 0x0c005000 0x0 0x00001000>;
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reg-names = "ecam", "xal", "xtl", "xtl-pri";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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linux,pci-domain = <0x00>;
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#interrupt-cells = <0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,
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<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,
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<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,
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<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;
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iommu-map = <0x0 &smmu2 0x10000 0x10000>;
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msi-map = <0x0 &its 0x210000 0x10000>;
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dma-coherent;
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ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,
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<0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,
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<0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;
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bus-range = <0x0 0xff>;
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nvidia,bpmp = <&bpmp 0>;
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};
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};
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pci@8400000 {
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compatible = "nvidia,tegra264-pcie";
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reg = <0xa8 0xb0000000 0x0 0x10000000>,
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<0x00 0x08400000 0x0 0x00004000>,
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<0x00 0x08404000 0x0 0x00001000>,
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<0x00 0x08405000 0x0 0x00001000>,
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<0x00 0x08410000 0x0 0x00010000>;
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reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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linux,pci-domain = <0x01>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,
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<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,
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<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,
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<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;
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iommu-map = <0x0 &smmu1 0x10000 0x10000>;
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msi-map = <0x0 &its 0x110000 0x10000>;
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dma-coherent;
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ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,
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<0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,
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<0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;
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bus-range = <0x00 0xff>;
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nvidia,bpmp = <&bpmp 1>;
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};
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};
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