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Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542766/ Signed-off-by: Rob Clark <robdclark@chromium.org>
96 lines
2.5 KiB
C
96 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
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#ifndef __A6XX_GPU_H__
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#define __A6XX_GPU_H__
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#include "adreno_gpu.h"
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#include "a6xx.xml.h"
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#include "a6xx_gmu.h"
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extern bool hang_debug;
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struct a6xx_gpu {
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struct adreno_gpu base;
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struct drm_gem_object *sqe_bo;
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uint64_t sqe_iova;
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struct msm_ringbuffer *cur_ring;
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struct a6xx_gmu gmu;
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struct drm_gem_object *shadow_bo;
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uint64_t shadow_iova;
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uint32_t *shadow;
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bool has_whereami;
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void __iomem *llc_mmio;
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void *llc_slice;
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void *htw_llc_slice;
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bool have_mmu500;
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bool hung;
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};
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#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
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/*
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* Given a register and a count, return a value to program into
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* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
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* registers starting at _reg.
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*/
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#define A6XX_PROTECT_NORDWR(_reg, _len) \
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((1 << 31) | \
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(((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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/*
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* Same as above, but allow reads over the range. For areas of mixed use (such
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* as performance counters) this allows us to protect a much larger range with a
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* single register
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*/
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#define A6XX_PROTECT_RDONLY(_reg, _len) \
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((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
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{
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if(adreno_is_a630(gpu))
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return false;
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return true;
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}
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#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
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((_ring)->id * sizeof(uint32_t)))
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int a6xx_gmu_resume(struct a6xx_gpu *gpu);
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int a6xx_gmu_stop(struct a6xx_gpu *gpu);
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int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
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bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
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int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
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int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
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void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
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void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
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bool suspended);
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unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
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void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
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struct drm_printer *p);
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struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
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int a6xx_gpu_state_put(struct msm_gpu_state *state);
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void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);
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void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
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#endif /* __A6XX_GPU_H__ */
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