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It turns out that in the CP110 HW block present in Marvell Armada 7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the GOP block. This commit updates the Device Tree binding for this piece of hardware accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
84 lines
2.7 KiB
Plaintext
84 lines
2.7 KiB
Plaintext
Marvell Armada CP110 System Controller 0
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========================================
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The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
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SoCs. It contains two sets of system control registers, System
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Controller 0 and System Controller 1. This Device Tree binding allows
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to describe the first system controller, which provides registers to
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configure various aspects of the SoC.
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The Device Tree node representing this System Controller 0 provides a
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number of clocks:
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- a set of core clocks
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- a set of gatable clocks
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Those clocks can be referenced by other Device Tree nodes using two
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cells:
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- The first cell must be 0 or 1. 0 for the core clocks and 1 for the
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gatable clocks.
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- The second cell identifies the particular core clock or gatable
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clocks.
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The following clocks are available:
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- Core clocks
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- 0 0 APLL
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- 0 1 PPv2 core
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- 0 2 EIP
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- 0 3 Core
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- 0 4 NAND core
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- Gatable clocks
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- 1 0 Audio
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- 1 1 Comm Unit
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- 1 2 NAND
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- 1 3 PPv2
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- 1 4 SDIO
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- 1 5 MG Domain
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- 1 6 MG Core
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- 1 7 XOR1
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- 1 8 XOR0
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- 1 9 GOP DP
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- 1 11 PCIe x1 0
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- 1 12 PCIe x1 1
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- 1 13 PCIe x4
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- 1 14 PCIe / XOR
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- 1 15 SATA
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- 1 16 SATA USB
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- 1 17 Main
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- 1 18 SD/MMC/GOP
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- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
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- 1 22 USB3H0
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- 1 23 USB3H1
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- 1 24 USB3 Device
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- 1 25 EIP150
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- 1 26 EIP197
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Required properties:
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- compatible: must be:
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"marvell,cp110-system-controller0", "syscon";
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- reg: register area of the CP110 system controller 0
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- #clock-cells: must be set to 2
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- core-clock-output-names must be set to:
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"cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
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- gate-clock-output-names must be set to:
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"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
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"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
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"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
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"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
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"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
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Example:
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cpm_syscon0: system-controller@440000 {
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compatible = "marvell,cp110-system-controller0", "syscon";
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reg = <0x440000 0x1000>;
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#clock-cells = <2>;
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core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
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gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
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"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
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"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
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"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
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"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
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};
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