mirror of
https://github.com/torvalds/linux.git
synced 2026-05-03 05:52:38 -04:00
2996148a9d
Pull dmaengine updates from Vinod Koul:
- updates to sprd, bam_dma, stm drivers
- remove VLAs in dmatest
- move TI drivers to their own subdir
- switch to SPDX tags for ima/mxs dma drivers
- simplify getting .drvdata on bunch of drivers by Wolfram Sang
* tag 'dmaengine-4.18-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (32 commits)
dmaengine: sprd: Add Spreadtrum DMA configuration
dmaengine: sprd: Optimize the sprd_dma_prep_dma_memcpy()
dmaengine: imx-dma: Switch to SPDX identifier
dmaengine: mxs-dma: Switch to SPDX identifier
dmaengine: imx-sdma: Switch to SPDX identifier
dmaengine: usb-dmac: Document R8A7799{0,5} bindings
dmaengine: qcom: bam_dma: fix some doc warnings.
dmaengine: qcom: bam_dma: fix invalid assignment warning
dmaengine: sprd: fix an NULL vs IS_ERR() bug
dmaengine: sprd: Use devm_ioremap_resource() to map memory
dmaengine: sprd: Fix potential NULL dereference in sprd_dma_probe()
dmaengine: pl330: flush before wait, and add dev burst support.
dmaengine: axi-dmac: Request IRQ with IRQF_SHARED
dmaengine: stm32-mdma: fix spelling mistake: "avalaible" -> "available"
dmaengine: rcar-dmac: Document R-Car D3 bindings
dmaengine: sprd: Move DMA request mode and interrupt type into head file
dmaengine: sprd: Define the DMA data width type
dmaengine: sprd: Define the DMA transfer step type
dmaengine: ti: New directory for Texas Instruments DMA drivers
dmaengine: shdmac: Change platform check to CONFIG_ARCH_RENESAS
...
112 lines
4.0 KiB
Plaintext
112 lines
4.0 KiB
Plaintext
* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
|
|
|
|
Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
|
|
controller instances named DMAC capable of serving multiple clients. Channels
|
|
can be dedicated to specific clients or shared between a large number of
|
|
clients.
|
|
|
|
Each DMA client is connected to one dedicated port of the DMAC, identified by
|
|
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
|
|
256 clients in total. When the number of hardware channels is lower than the
|
|
number of clients to be served, channels must be shared between multiple DMA
|
|
clients. The association of DMA clients to DMAC channels is fully dynamic and
|
|
not described in these device tree bindings.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
|
|
Examples with soctypes are:
|
|
- "renesas,dmac-r8a7743" (RZ/G1M)
|
|
- "renesas,dmac-r8a7745" (RZ/G1E)
|
|
- "renesas,dmac-r8a77470" (RZ/G1C)
|
|
- "renesas,dmac-r8a7790" (R-Car H2)
|
|
- "renesas,dmac-r8a7791" (R-Car M2-W)
|
|
- "renesas,dmac-r8a7792" (R-Car V2H)
|
|
- "renesas,dmac-r8a7793" (R-Car M2-N)
|
|
- "renesas,dmac-r8a7794" (R-Car E2)
|
|
- "renesas,dmac-r8a7795" (R-Car H3)
|
|
- "renesas,dmac-r8a7796" (R-Car M3-W)
|
|
- "renesas,dmac-r8a77965" (R-Car M3-N)
|
|
- "renesas,dmac-r8a77970" (R-Car V3M)
|
|
- "renesas,dmac-r8a77980" (R-Car V3H)
|
|
- "renesas,dmac-r8a77995" (R-Car D3)
|
|
|
|
- reg: base address and length of the registers block for the DMAC
|
|
|
|
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
|
interrupt-names.
|
|
- interrupt-names: one entry for the error interrupt, named "error", plus one
|
|
entry per channel, named "ch%u", where %u is the channel number ranging from
|
|
zero to the number of channels minus one.
|
|
|
|
- clock-names: "fck" for the functional clock
|
|
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
|
in clock-names.
|
|
- clock-names: must contain "fck" for the functional clock.
|
|
|
|
- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
|
|
connected to the DMA client
|
|
- dma-channels: number of DMA channels
|
|
|
|
Example: R8A7790 (R-Car H2) SYS-DMACs
|
|
|
|
dmac0: dma-controller@e6700000 {
|
|
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
|
reg = <0 0xe6700000 0 0x20000>;
|
|
interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
|
|
0 200 IRQ_TYPE_LEVEL_HIGH
|
|
0 201 IRQ_TYPE_LEVEL_HIGH
|
|
0 202 IRQ_TYPE_LEVEL_HIGH
|
|
0 203 IRQ_TYPE_LEVEL_HIGH
|
|
0 204 IRQ_TYPE_LEVEL_HIGH
|
|
0 205 IRQ_TYPE_LEVEL_HIGH
|
|
0 206 IRQ_TYPE_LEVEL_HIGH
|
|
0 207 IRQ_TYPE_LEVEL_HIGH
|
|
0 208 IRQ_TYPE_LEVEL_HIGH
|
|
0 209 IRQ_TYPE_LEVEL_HIGH
|
|
0 210 IRQ_TYPE_LEVEL_HIGH
|
|
0 211 IRQ_TYPE_LEVEL_HIGH
|
|
0 212 IRQ_TYPE_LEVEL_HIGH
|
|
0 213 IRQ_TYPE_LEVEL_HIGH
|
|
0 214 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14";
|
|
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
|
clock-names = "fck";
|
|
#dma-cells = <1>;
|
|
dma-channels = <15>;
|
|
};
|
|
|
|
dmac1: dma-controller@e6720000 {
|
|
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
|
reg = <0 0xe6720000 0 0x20000>;
|
|
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
|
|
0 216 IRQ_TYPE_LEVEL_HIGH
|
|
0 217 IRQ_TYPE_LEVEL_HIGH
|
|
0 218 IRQ_TYPE_LEVEL_HIGH
|
|
0 219 IRQ_TYPE_LEVEL_HIGH
|
|
0 308 IRQ_TYPE_LEVEL_HIGH
|
|
0 309 IRQ_TYPE_LEVEL_HIGH
|
|
0 310 IRQ_TYPE_LEVEL_HIGH
|
|
0 311 IRQ_TYPE_LEVEL_HIGH
|
|
0 312 IRQ_TYPE_LEVEL_HIGH
|
|
0 313 IRQ_TYPE_LEVEL_HIGH
|
|
0 314 IRQ_TYPE_LEVEL_HIGH
|
|
0 315 IRQ_TYPE_LEVEL_HIGH
|
|
0 316 IRQ_TYPE_LEVEL_HIGH
|
|
0 317 IRQ_TYPE_LEVEL_HIGH
|
|
0 318 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14";
|
|
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
|
clock-names = "fck";
|
|
#dma-cells = <1>;
|
|
dma-channels = <15>;
|
|
};
|