mirror of
https://github.com/torvalds/linux.git
synced 2026-04-27 19:12:29 -04:00
892204e06c
Pull MIPS updates from James Hogan:
"These are the main MIPS changes for 4.15.
Fixes:
- ralink: Fix MT7620 PCI build issues (4.5)
- Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP
(4.1)
- Fix MIPS64 FP save/restore on 32-bit kernels (4.0)
- ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19)
- ralink: Fix MT7628 pinmux (3.19)
- BCM47XX: Fix LED inversion on WRT54GSv1 (3.17)
- Fix n32 core dumping as o32 since regset support (3.13)
- ralink: Drop obsolete USB_ARCH_HAS_HCD select
Build system:
- Default to "generic" (multiplatform) system type instead of IP22
- Use generic little endian MIPS32 r2 configuration as default
defconfig instead of ip22_defconfig
FPU emulation:
- Fix exception generation for certain R6 FPU instructions
SMP:
- Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id
spaces
Miscellaneous:
- Add iomem resource for kernel bss section for kexec/kdump
- Atomics: Nudge writes on bit unlock
- DT files: Standardise "ok" -> "okay"
Minor cleanups:
- Define virt_to_pfn()
- Make thread_saved_pc static
- Simplify 32-bit sign extension in __read_64bit_c0_split()
- DMA: Use vma_pages() helper
- FPU emulation: Replace unsigned with unsigned int
- MM: Removed unused lastpfn
- Alchemy: Make clk_ops const
- Lasat: Use setup_timer() helper
- ralink: Use BIT() in MT7620 PCI driver
Platform support:
BMIPS:
- Enable HARDIRQS_SW_RESEND
Broadcom BCM63XX:
- Add clkdev lookup support
- Update clk driver, UART driver, DTs to handle named refclk from DTs
- Split apart various clocks to more closely match hardware
- Add ethernet clocks
Cavium Octeon:
- Remove usage of cvmx_wait() in favour of __delay()
ImgTec Pistachio:
- DT: Drop deprecated dwmmc num-slots property
Ingenic JZ4780:
- Add NFS root to Ci20 defconfig
- Add watchdog to Ci20 DT & defconfig, and allow building of watchdog
driver with this SoC
Generic (multiplatform):
- Migrate xilfpga (MIPSfpga) platform to the generic platform
Lantiq xway:
- Fix ASC0/ASC1 clocks"
* tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (46 commits)
MIPS: Add iomem resource for kernel bss section.
MIPS: cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN don't work for 32-bit SMP
MIPS: BMIPS: Enable HARDIRQS_SW_RESEND
MIPS: pci: Make use of the BIT() macro inside the mt7620 driver
MIPS: pci: Remove KERN_WARN instance inside the mt7620 driver
MIPS: pci: Remove duplicate define in mt7620 driver
MIPS: ralink: Fix typo in mt7628 pinmux function
MIPS: ralink: Fix MT7628 pinmux
MIPS: Fix odd fp register warnings with MIPS64r2
watchdog: jz4780: Allow selection of jz4740-wdt driver
MIPS/ptrace: Update syscall nr on register changes
MIPS/ptrace: Pick up ptrace/seccomp changed syscalls
MIPS: Fix an n32 core file generation regset support regression
MIPS: Fix MIPS64 FP save/restore on 32-bit kernels
MIPS: page.h: Define virt_to_pfn()
MIPS: Xilfpga: Switch to using generic defconfigs
MIPS: generic: Add support for MIPSfpga
MIPS: Set defconfig target to a generic system for 32r2el
MIPS: Kconfig: Set default MIPS system type as generic
MIPS: DTS: Remove num-slots from Pistachio SoC
...
253 lines
4.6 KiB
Plaintext
253 lines
4.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
#include <dt-bindings/clock/jz4780-cgu.h>
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "ingenic,jz4780";
|
|
|
|
cpuintc: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
};
|
|
|
|
intc: interrupt-controller@10001000 {
|
|
compatible = "ingenic,jz4780-intc";
|
|
reg = <0x10001000 0x50>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
};
|
|
|
|
ext: ext {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rtc: rtc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
cgu: jz4780-cgu@10000000 {
|
|
compatible = "ingenic,jz4780-cgu";
|
|
reg = <0x10000000 0x100>;
|
|
|
|
clocks = <&ext>, <&rtc>;
|
|
clock-names = "ext", "rtc";
|
|
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
rtc_dev: rtc@10003000 {
|
|
compatible = "ingenic,jz4780-rtc";
|
|
reg = <0x10003000 0x4c>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <32>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_RTCLK>;
|
|
clock-names = "rtc";
|
|
};
|
|
|
|
pinctrl: pin-controller@10010000 {
|
|
compatible = "ingenic,jz4780-pinctrl";
|
|
reg = <0x10010000 0x600>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gpa: gpio@0 {
|
|
compatible = "ingenic,jz4780-gpio";
|
|
reg = <0>;
|
|
|
|
gpio-controller;
|
|
gpio-ranges = <&pinctrl 0 0 32>;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <17>;
|
|
};
|
|
|
|
gpb: gpio@1 {
|
|
compatible = "ingenic,jz4780-gpio";
|
|
reg = <1>;
|
|
|
|
gpio-controller;
|
|
gpio-ranges = <&pinctrl 0 32 32>;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <16>;
|
|
};
|
|
|
|
gpc: gpio@2 {
|
|
compatible = "ingenic,jz4780-gpio";
|
|
reg = <2>;
|
|
|
|
gpio-controller;
|
|
gpio-ranges = <&pinctrl 0 64 32>;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <15>;
|
|
};
|
|
|
|
gpd: gpio@3 {
|
|
compatible = "ingenic,jz4780-gpio";
|
|
reg = <3>;
|
|
|
|
gpio-controller;
|
|
gpio-ranges = <&pinctrl 0 96 32>;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <14>;
|
|
};
|
|
|
|
gpe: gpio@4 {
|
|
compatible = "ingenic,jz4780-gpio";
|
|
reg = <4>;
|
|
|
|
gpio-controller;
|
|
gpio-ranges = <&pinctrl 0 128 32>;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <13>;
|
|
};
|
|
|
|
gpf: gpio@5 {
|
|
compatible = "ingenic,jz4780-gpio";
|
|
reg = <5>;
|
|
|
|
gpio-controller;
|
|
gpio-ranges = <&pinctrl 0 160 32>;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <12>;
|
|
};
|
|
};
|
|
|
|
uart0: serial@10030000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10030000 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <51>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@10031000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10031000 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <50>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@10032000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10032000 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <49>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@10033000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10033000 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <48>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@10034000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10034000 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <34>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog: watchdog@10002000 {
|
|
compatible = "ingenic,jz4780-watchdog";
|
|
reg = <0x10002000 0x100>;
|
|
};
|
|
|
|
nemc: nemc@13410000 {
|
|
compatible = "ingenic,jz4780-nemc";
|
|
reg = <0x13410000 0x10000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <1 0 0x1b000000 0x1000000
|
|
2 0 0x1a000000 0x1000000
|
|
3 0 0x19000000 0x1000000
|
|
4 0 0x18000000 0x1000000
|
|
5 0 0x17000000 0x1000000
|
|
6 0 0x16000000 0x1000000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_NEMC>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
bch: bch@134d0000 {
|
|
compatible = "ingenic,jz4780-bch";
|
|
reg = <0x134d0000 0x10000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_BCH>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|