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6c22ea3747
These exist to give NVKM information on the set of display paths that the DD needs to be active at any given time. Previously, the supervisor attempted to determine this solely from OR state, but there's a few configurations where this information on its own isn't enough to determine the specific display paths in question: - ANX9805, where the PIOR protocol for both DP and TMDS is TMDS. - On a device using DCB Switched Outputs. - On GM20x and newer, with a crossbar between the SOR and macro links. After this commit, the DD tells NVKM *exactly* which display path it's attempting a modeset on. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/*
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* Copyright 2016 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "nv50.h"
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#include "head.h"
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#include "ior.h"
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#include "rootnv50.h"
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static void
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gp102_disp_intr_error(struct nv50_disp *disp, int chid)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
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u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
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u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12));
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nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
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chid, (mthd & 0x0000ffc), data, mthd, unkn);
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if (chid < ARRAY_SIZE(disp->chan)) {
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switch (mthd & 0xffc) {
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case 0x0080:
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nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
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break;
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default:
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break;
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}
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}
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nvkm_wr32(device, 0x61009c, (1 << chid));
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nvkm_wr32(device, 0x6111f0 + (chid * 12), 0x90000000);
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}
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static const struct nv50_disp_func
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gp102_disp = {
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.intr = gf119_disp_intr,
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.intr_error = gp102_disp_intr_error,
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.uevent = &gf119_disp_chan_uevent,
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.super = gf119_disp_super,
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.root = &gp102_disp_root_oclass,
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.head.new = gf119_head_new,
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.sor = { .nr = 4, .new = gm200_sor_new },
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};
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int
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gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
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{
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return gf119_disp_new_(&gp102_disp, device, index, pdisp);
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}
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