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358b3774a0
Add register list and enable devcoredump for JPEG5_0_1 V2: (Lijo) - remove version specific callbacks and use simplified helper functions V3: (Lijo) - move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
91 lines
4.5 KiB
C
91 lines
4.5 KiB
C
/*
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* Copyright 2024 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __JPEG_V5_0_1_H__
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#define __JPEG_V5_0_1_H__
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extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block;
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#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640
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#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1
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#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649
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#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1
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#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a
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#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1
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#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x0000
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#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC1_UVD_JRBC_STATUS 0x0009
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#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x000a
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#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0040
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#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0049
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#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x004a
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#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0080
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#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0089
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#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x008a
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#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC4_UVD_JRBC_RB_WPTR 0x00c0
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#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC4_UVD_JRBC_STATUS 0x00c9
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#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC4_UVD_JRBC_RB_RPTR 0x00ca
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#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC5_UVD_JRBC_RB_WPTR 0x0100
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#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC5_UVD_JRBC_STATUS 0x0109
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#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC5_UVD_JRBC_RB_RPTR 0x010a
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#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC6_UVD_JRBC_RB_WPTR 0x0140
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#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC6_UVD_JRBC_STATUS 0x0149
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#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC6_UVD_JRBC_RB_RPTR 0x014a
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#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC7_UVD_JRBC_RB_WPTR 0x0180
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#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC7_UVD_JRBC_STATUS 0x0189
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#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC7_UVD_JRBC_RB_RPTR 0x018a
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#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC8_UVD_JRBC_RB_WPTR 0x01c0
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#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX 0
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#define regUVD_JRBC8_UVD_JRBC_STATUS 0x01c9
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#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX 0
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#define regUVD_JRBC8_UVD_JRBC_RB_RPTR 0x01ca
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#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX 0
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#define regUVD_JRBC9_UVD_JRBC_RB_WPTR 0x0440
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#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX 1
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#define regUVD_JRBC9_UVD_JRBC_STATUS 0x0449
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#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX 1
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#define regUVD_JRBC9_UVD_JRBC_RB_RPTR 0x044a
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#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX 1
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#endif /* __JPEG_V5_0_0_H__ */
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