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Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where CBR(Core Base Register) address might be badly or never initialized by the Bootloader or reading it from co-processor registers, if the system boots from secondary CPU, results in invalid address. The CBR address is always the same on the SoC. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
121 lines
2.8 KiB
YAML
121 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mips/brcm/soc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom cable/DSL/settop platforms
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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description: |
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Boards Broadcom cable/DSL/settop SoC shall have the following properties.
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The experimental -viper variants are for running Linux on the 3384's
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BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
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properties:
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$nodename:
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const: '/'
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compatible:
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enum:
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- brcm,bcm3368
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- brcm,bcm3384
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- brcm,bcm33843
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- brcm,bcm3384-viper
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- brcm,bcm33843-viper
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- brcm,bcm6328
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- brcm,bcm6358
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- brcm,bcm6362
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- brcm,bcm6368
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- brcm,bcm63168
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- brcm,bcm63268
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- brcm,bcm7125
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- brcm,bcm7346
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- brcm,bcm7358
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- brcm,bcm7360
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- brcm,bcm7362
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- brcm,bcm7420
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- brcm,bcm7425
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cpus:
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type: object
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additionalProperties: false
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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mips-hpt-frequency:
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description: MIPS counter high precision timer frequency.
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This is common to all CPUs in the system so it lives
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under the "cpus" node.
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$ref: /schemas/types.yaml#/definitions/uint32
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brcm,bmips-cbr-reg:
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description: Reference address of the CBR.
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Some SoC suffer from a BUG where CBR(Core Base Register)
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address might be badly or never initialized by the Bootloader
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or reading it from co-processor registers, if the system boots
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from secondary CPU, results in invalid address.
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The CBR address is always the same on the SoC hence it
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can be provided in DT to handle these broken case.
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$ref: /schemas/types.yaml#/definitions/uint32
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patternProperties:
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"^cpu@[0-9]$":
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type: object
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$ref: /schemas/mips/cpus.yaml#
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unevaluatedProperties: false
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required:
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- mips-hpt-frequency
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if:
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properties:
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compatible:
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contains:
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enum:
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- brcm,bcm6358
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- brcm,bcm6368
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then:
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properties:
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cpus:
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required:
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- brcm,bmips-cbr-reg
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additionalProperties: true
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examples:
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- |
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/ {
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compatible = "brcm,bcm3368";
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Broadcom 3368";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <150000000>;
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cpu@0 {
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compatible = "brcm,bmips4350";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "brcm,bmips4350";
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device_type = "cpu";
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reg = <1>;
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};
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};
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};
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...
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