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The 'phandle-array' type is a bit ambiguous. It can be either just an
array of phandles or an array of phandles plus args. Many schemas for
phandle-array properties aren't clear in the schema which case applies
though the description usually describes it.
The array of phandles case boils down to needing:
items:
maxItems: 1
The phandle plus args cases should typically take this form:
items:
- items:
- description: A phandle
- description: 1st arg cell
- description: 2nd arg cell
With this change, some examples need updating so that the bracketing of
property values matches the schema.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20220119015038.2433585-1-robh@kernel.org
110 lines
3.4 KiB
YAML
110 lines
3.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Performance Monitor Units
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maintainers:
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- Mark Rutland <mark.rutland@arm.com>
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- Will Deacon <will.deacon@arm.com>
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description: |+
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ARM cores often have a PMU for counting cpu and cache events like cache misses
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and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
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representation in the device tree should be done as under:-
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properties:
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compatible:
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items:
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- enum:
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- apm,potenza-pmu
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- arm,armv8-pmuv3 # Only for s/w models
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- arm,arm1136-pmu
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- arm,arm1176-pmu
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- arm,arm11mpcore-pmu
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- arm,cortex-a5-pmu
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- arm,cortex-a7-pmu
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- arm,cortex-a8-pmu
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- arm,cortex-a9-pmu
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- arm,cortex-a12-pmu
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- arm,cortex-a15-pmu
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- arm,cortex-a17-pmu
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- arm,cortex-a32-pmu
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- arm,cortex-a34-pmu
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- arm,cortex-a35-pmu
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- arm,cortex-a53-pmu
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- arm,cortex-a55-pmu
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- arm,cortex-a57-pmu
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- arm,cortex-a65-pmu
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- arm,cortex-a72-pmu
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- arm,cortex-a73-pmu
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- arm,cortex-a75-pmu
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- arm,cortex-a76-pmu
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- arm,cortex-a77-pmu
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- arm,cortex-a78-pmu
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- arm,cortex-a510-pmu
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- arm,cortex-a710-pmu
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- arm,cortex-x1-pmu
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- arm,cortex-x2-pmu
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- arm,neoverse-e1-pmu
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- arm,neoverse-n1-pmu
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- arm,neoverse-n2-pmu
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- arm,neoverse-v1-pmu
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- brcm,vulcan-pmu
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- cavium,thunder-pmu
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- nvidia,denver-pmu
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- nvidia,carmel-pmu
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- qcom,krait-pmu
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- qcom,scorpion-pmu
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- qcom,scorpion-mp-pmu
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interrupts:
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# Don't know how many CPUs, so no constraints to specify
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description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
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interrupt-affinity:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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maxItems: 1
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description:
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When using SPIs, specifies a list of phandles to CPU
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nodes corresponding directly to the affinity of
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the SPIs listed in the interrupts property.
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When using a PPI, specifies a list of phandles to CPU
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nodes corresponding to the set of CPUs which have
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a PMU of this type signalling the PPI listed in the
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interrupts property, unless this is already specified
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by the PPI interrupt specifier itself (in which case
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the interrupt-affinity property shouldn't be present).
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This property should be present when there is more than
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a single SPI.
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qcom,no-pc-write:
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type: boolean
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description:
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Indicates that this PMU doesn't support the 0xc and 0xd events.
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secure-reg-access:
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type: boolean
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description:
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Indicates that the ARMv7 Secure Debug Enable Register
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(SDER) is accessible. This will cause the driver to do
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any setup required that is only possible in ARMv7 secure
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state. If not present the ARMv7 SDER will not be touched,
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which means the PMU may fail to operate unless external
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code (bootloader or security monitor) has performed the
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appropriate initialisation. Note that this property is
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not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
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in Non-secure state.
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required:
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- compatible
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additionalProperties: false
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...
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