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QMP PCI PHY PIPE clocks are inputs for the GCC clock controller. In order to describe this in DTS, allow passing them as the inputs to GCC. This has a benefit that it avoids doing a global matching by name. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231013164025.3541606-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
55 lines
1.1 KiB
YAML
55 lines
1.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on IPQ8074
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on IPQ8074.
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See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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const: qcom,gcc-ipq8074
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clocks:
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items:
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- description: board XO clock
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- description: sleep clock
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- description: Gen3 QMP PCIe PHY PIPE clock
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- description: Gen2 QMP PCIe PHY PIPE clock
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clock-names:
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items:
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- const: xo
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- const: sleep_clk
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- const: pcie0_pipe
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- const: pcie1_pipe
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-ipq8074";
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reg = <0x01800000 0x80000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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...
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