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5db62b7d3c
dtschema package with core schemas deprecated pci-bus.yaml schema in favor of pci-host-bridge.yaml. Update all bindings to use the latter one. The difference between pci-bus.yaml and pci-host-bridge.yaml is only in lack of "reg" property defined by the latter, which should not have any effect here, because all these bindings define the "reg". The change is therefore quite trivial, however it requires dtschema package v2024.02 or newer. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # Renesas Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
667 lines
17 KiB
YAML
667 lines
17 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCI express root complex
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description: |
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Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
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PCIe IP.
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,pcie-apq8064
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- qcom,pcie-apq8084
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- qcom,pcie-ipq4019
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064-v2
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- qcom,pcie-ipq8074
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-msm8996
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- qcom,pcie-qcs404
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- qcom,pcie-sdm845
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- qcom,pcie-sdx55
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- items:
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- const: qcom,pcie-msm8998
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- const: qcom,pcie-msm8996
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reg:
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minItems: 4
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maxItems: 6
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reg-names:
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minItems: 4
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maxItems: 6
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interrupts:
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minItems: 1
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maxItems: 8
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interrupt-names:
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minItems: 1
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maxItems: 8
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iommu-map:
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minItems: 1
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maxItems: 16
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# Common definitions for clocks, clock-names and reset.
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# Platform constraints are described later.
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clocks:
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minItems: 3
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maxItems: 13
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clock-names:
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minItems: 3
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maxItems: 13
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dma-coherent: true
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: pcie-mem
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- const: cpu-pcie
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resets:
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minItems: 1
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maxItems: 12
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reset-names:
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minItems: 1
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maxItems: 12
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vdda-supply:
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description: A phandle to the core analog power supply
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vdda_phy-supply:
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description: A phandle to the core analog power supply for PHY
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vdda_refclk-supply:
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description: A phandle to the core analog power supply for IC which generates reference clock
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pciephy
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power-domains:
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maxItems: 1
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perst-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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required-opps:
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maxItems: 1
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wake-gpios:
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description: GPIO controlled connection to WAKE# signal
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupt-map-mask
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- interrupt-map
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- clocks
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- clock-names
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anyOf:
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- required:
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- required:
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- msi-map
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8064
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- qcom,pcie-ipq4019
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064v2
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- qcom,pcie-ipq8074
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- qcom,pcie-qcs404
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then:
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properties:
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reg:
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minItems: 4
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maxItems: 4
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reg-names:
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items:
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: parf # Qualcomm specific registers
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- const: config # PCIe configuration space
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8074-gen3
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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reg-names:
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items:
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: parf # Qualcomm specific registers
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- const: config # PCIe configuration space
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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- qcom,pcie-msm8996
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- qcom,pcie-sdm845
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then:
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properties:
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sdx55
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8064
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064v2
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 5
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clock-names:
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minItems: 3
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items:
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- const: core # Clocks the pcie hw block
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- const: iface # Configuration AHB clock
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- const: phy # Clocks the pcie PHY block
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- const: aux # Clocks the pcie AUX block, not on apq8064
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- const: ref # Clocks the pcie ref block, not on apq8064
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resets:
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minItems: 5
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maxItems: 6
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reset-names:
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minItems: 5
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items:
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- const: axi # AXI reset
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- const: ahb # AHB reset
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- const: por # POR reset
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- const: pci # PCI reset
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- const: phy # PHY reset
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- const: ext # EXT reset, not on apq8064
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required:
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- vdda-supply
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- vdda_phy-supply
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- vdda_refclk-supply
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: iface # Configuration AHB clock
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- const: master_bus # Master AXI clock
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- const: slave_bus # Slave AXI clock
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- const: aux # Auxiliary (AUX) clock
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: core # Core reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq4019
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: aux # Auxiliary (AUX) clock
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- const: master_bus # Master AXI clock
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- const: slave_bus # Slave AXI clock
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resets:
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minItems: 12
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maxItems: 12
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reset-names:
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items:
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- const: axi_m # AXI master reset
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- const: axi_s # AXI slave reset
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- const: pipe # PIPE reset
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- const: axi_m_vmid # VMID reset
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- const: axi_s_xpu # XPU reset
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- const: parf # PARF reset
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- const: phy # PHY reset
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- const: axi_m_sticky # AXI sticky reset
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- const: pipe_sticky # PIPE sticky reset
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- const: pwr # PWR reset
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- const: ahb # AHB reset
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- const: phy_ahb # PHY AHB reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-msm8996
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: pipe # Pipe Clock driving internal logic
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- const: aux # Auxiliary (AUX) clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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resets: false
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reset-names: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq8074
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: ahb # AHB clock
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- const: aux # Auxiliary clock
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resets:
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minItems: 7
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maxItems: 7
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sleep # Sleep reset
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- const: sticky # Core Sticky reset
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: ahb # AHB Reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8074-gen3
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: axi_bridge # AXI bridge clock
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- const: rchng
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resets:
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minItems: 8
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maxItems: 8
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sleep # Sleep reset
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- const: sticky # Core Sticky reset
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: ahb # AHB Reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: axi_s_sticky # AXI Slave Sticky reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-qcs404
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: iface # AHB clock
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- const: aux # Auxiliary clock
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- const: master_bus # AXI Master clock
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- const: slave_bus # AXI Slave clock
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resets:
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minItems: 6
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maxItems: 6
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reset-names:
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items:
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: pipe_sticky # PIPE sticky reset
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- const: pwr # PWR reset
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- const: ahb # AHB reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sdm845
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then:
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oneOf:
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# Unfortunately the "optional" ref clock is used in the middle of the list
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- properties:
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: ref # REFERENCE clock
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- const: tbu # PCIe TBU clock
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- properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: tbu # PCIe TBU clock
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properties:
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci # PCIe core reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sdx55
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: sleep # PCIe Sleep clock
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci # PCIe core reset
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8064
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- qcom,pcie-ipq4019
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064v2
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- qcom,pcie-ipq8074
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-qcs404
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then:
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required:
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- power-domains
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-msm8996
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then:
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required:
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- resets
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- reset-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-msm8996
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- qcom,pcie-sdm845
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then:
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oneOf:
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- properties:
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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- properties:
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interrupts:
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minItems: 8
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8064
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- qcom,pcie-apq8084
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- qcom,pcie-ipq4019
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064-v2
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- qcom,pcie-ipq8074
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-qcs404
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then:
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properties:
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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unevaluatedProperties: false
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|
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@1b500000 {
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compatible = "qcom,pcie-ipq8064";
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reg = <0x1b500000 0x1000>,
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<0x1b502000 0x80>,
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<0x1b600000 0x100>,
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<0x0ff00000 0x100000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
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<0x82000000 0 0 0x08000000 0 0x07e00000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc 41>,
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<&gcc 43>,
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<&gcc 44>,
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<&gcc 42>,
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<&gcc 248>;
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clock-names = "core", "iface", "phy", "aux", "ref";
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resets = <&gcc 27>,
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<&gcc 26>,
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<&gcc 25>,
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<&gcc 24>,
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<&gcc 23>,
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<&gcc 22>;
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reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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pinctrl-0 = <&pcie_pins_default>;
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pinctrl-names = "default";
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vdda-supply = <&pm8921_s3>;
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vdda_phy-supply = <&pm8921_lvs6>;
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vdda_refclk-supply = <&ext_3p3v>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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pcie@fc520000 {
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compatible = "qcom,pcie-apq8084";
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reg = <0xfc520000 0x2000>,
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<0xff000000 0x1000>,
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<0xff001000 0x1000>,
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<0xff002000 0x2000>;
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reg-names = "parf", "dbi", "elbi", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
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<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc 324>,
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<&gcc 325>,
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<&gcc 327>,
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<&gcc 323>;
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clock-names = "iface", "master_bus", "slave_bus", "aux";
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resets = <&gcc 81>;
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reset-names = "core";
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power-domains = <&gcc 1>;
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vdda-supply = <&pma8084_l3>;
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phys = <&pciephy0>;
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phy-names = "pciephy";
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perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_pins_default>;
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pinctrl-names = "default";
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};
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...
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