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1238913f24
The servers for the @codeaurora domain are long retired and any messages sent there will bounce. Sai has left the company and appears no longer active in the community which leaves this binding orphaned. Rajendra Nayak has volunteered to take over as maintainer. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rajendra Nayak <quic_rjendra@quicinc.com> Link: https://lore.kernel.org/r/20240223161455.4009469-1-quic_jhugo@quicinc.com Signed-off-by: Rob Herring <robh@kernel.org>
146 lines
3.9 KiB
YAML
146 lines
3.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
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maintainers:
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- Rajendra Nayak <quic_rjendra@quicinc.com>
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properties:
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$nodename:
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pattern: "^(watchdog|timer)@[0-9a-f]+$"
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,kpss-wdt-ipq4019
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- qcom,apss-wdt-ipq5018
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- qcom,apss-wdt-ipq5332
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- qcom,apss-wdt-ipq9574
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- qcom,apss-wdt-msm8226
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- qcom,apss-wdt-msm8974
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- qcom,apss-wdt-msm8994
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- qcom,apss-wdt-qcm2290
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- qcom,apss-wdt-qcs404
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- qcom,apss-wdt-sa8775p
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- qcom,apss-wdt-sc7180
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- qcom,apss-wdt-sc7280
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- qcom,apss-wdt-sc8180x
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- qcom,apss-wdt-sc8280xp
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- qcom,apss-wdt-sdm845
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- qcom,apss-wdt-sdx55
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- qcom,apss-wdt-sdx65
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- qcom,apss-wdt-sm6115
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- qcom,apss-wdt-sm6350
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- qcom,apss-wdt-sm8150
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- qcom,apss-wdt-sm8250
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- const: qcom,kpss-wdt
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- const: qcom,kpss-wdt
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deprecated: true
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- items:
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- const: qcom,scss-timer
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- const: qcom,msm-timer
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- items:
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- enum:
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- qcom,kpss-wdt-apq8064
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- qcom,kpss-wdt-ipq8064
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- qcom,kpss-wdt-mdm9615
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- qcom,kpss-wdt-msm8960
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- const: qcom,kpss-timer
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- const: qcom,msm-timer
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: sleep
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clock-frequency:
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description:
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The frequency of the general purpose timer in Hz.
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cpu-offset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Per-CPU offset used when the timer is accessed without the CPU remapping
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facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
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interrupts:
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minItems: 1
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maxItems: 5
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required:
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- compatible
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- reg
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- clocks
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allOf:
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- $ref: watchdog.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: qcom,kpss-wdt
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then:
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properties:
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clock-frequency: false
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cpu-offset: false
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interrupts:
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minItems: 1
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items:
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- description: Bark
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- description: Bite
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else:
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properties:
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interrupts:
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minItems: 3
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items:
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- description: Debug
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- description: First general purpose timer
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- description: Second general purpose timer
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- description: First watchdog
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- description: Second watchdog
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required:
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- clock-frequency
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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watchdog@17c10000 {
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compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
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reg = <0x17c10000 0x1000>;
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clocks = <&sleep_clk>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
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timeout-sec = <10>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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watchdog@200a000 {
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compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <25000000>;
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clocks = <&sleep_clk>;
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clock-names = "sleep";
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cpu-offset = <0x80000>;
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};
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