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phy: lynx-28g: remove LYNX_28G_ prefix from register names
Currently, in macros such as lynx_28g_lane_rmw(), the driver has macros which concatenate the LYNX_28G_ prefix with the "val" and "mask" arguments. This is done to shorten function calls and not have to spell out LYNX_28G_ everywhere. But outside of lynx_28g_lane_rmw(), lynx_28g_lane_read() and lynx_28g_pll_read(), this is not done, leading to an inconsistency in the code. Also, the concatenation itself has the disadvantage that searching the arguments of these functions as full words (like N_RATE_QUARTER) leads us nowhere, since the real macro definition is LNaTGCR0_N_RATE_QUARTER. Some maintainers want register definitions in drivers to contain the driver name as a prefix, but here, this has the disadvantages listed above, so just remove that prefix. The only change made here is the removal of LYNX_28G_. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-6-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Vladimir Oltean
committed by
Vinod Koul
Vinod Koul
parent
2da0b2214f
commit
13a5f7e3fd
@@ -12,99 +12,99 @@
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#define LYNX_28G_NUM_PLL 2
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/* General registers per SerDes block */
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#define LYNX_28G_PCC8 0x10a0
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#define LYNX_28G_PCC8_SGMII 0x1
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#define LYNX_28G_PCC8_SGMII_DIS 0x0
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#define PCC8 0x10a0
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#define PCC8_SGMII 0x1
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#define PCC8_SGMII_DIS 0x0
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#define LYNX_28G_PCCC 0x10b0
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#define LYNX_28G_PCCC_10GBASER 0x9
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#define LYNX_28G_PCCC_USXGMII 0x1
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#define LYNX_28G_PCCC_SXGMII_DIS 0x0
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#define PCCC 0x10b0
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#define PCCC_10GBASER 0x9
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#define PCCC_USXGMII 0x1
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#define PCCC_SXGMII_DIS 0x0
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#define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
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#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
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/* Per PLL registers */
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#define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
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#define LYNX_28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
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#define LYNX_28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
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#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
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#define PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
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#define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
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#define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
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#define LYNX_28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
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#define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
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#define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
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#define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
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#define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
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#define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
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#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
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#define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
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#define PLLnCR0_REFCLK_SEL_100MHZ 0x0
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#define PLLnCR0_REFCLK_SEL_125MHZ 0x10000
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#define PLLnCR0_REFCLK_SEL_156MHZ 0x20000
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#define PLLnCR0_REFCLK_SEL_150MHZ 0x30000
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#define PLLnCR0_REFCLK_SEL_161MHZ 0x40000
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#define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
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#define LYNX_28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
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#define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0
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#define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
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#define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
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#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
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#define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
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#define PLLnCR1_FRATE_5G_10GVCO 0x0
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#define PLLnCR1_FRATE_5G_25GVCO 0x10000000
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#define PLLnCR1_FRATE_10G_20GVCO 0x6000000
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/* Per SerDes lane registers */
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/* Lane a General Control Register */
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#define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
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#define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
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#define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8
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#define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50
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#define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
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#define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
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#define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
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#define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
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#define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
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#define LNaGCR0_PROTO_SEL_SGMII 0x8
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#define LNaGCR0_PROTO_SEL_XFI 0x50
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#define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
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#define LNaGCR0_IF_WIDTH_10_BIT 0x0
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#define LNaGCR0_IF_WIDTH_20_BIT 0x2
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/* Lane a Tx Reset Control Register */
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#define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
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#define LYNX_28G_LNaTRSTCTL_HLT_REQ BIT(27)
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#define LYNX_28G_LNaTRSTCTL_RST_DONE BIT(30)
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#define LYNX_28G_LNaTRSTCTL_RST_REQ BIT(31)
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#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
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#define LNaTRSTCTL_HLT_REQ BIT(27)
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#define LNaTRSTCTL_RST_DONE BIT(30)
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#define LNaTRSTCTL_RST_REQ BIT(31)
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/* Lane a Tx General Control Register */
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#define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
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#define LYNX_28G_LNaTGCR0_USE_PLLF 0x0
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#define LYNX_28G_LNaTGCR0_USE_PLLS BIT(28)
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#define LYNX_28G_LNaTGCR0_USE_PLL_MSK BIT(28)
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#define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0
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#define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000
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#define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
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#define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
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#define LNaTGCR0_USE_PLLF 0x0
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#define LNaTGCR0_USE_PLLS BIT(28)
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#define LNaTGCR0_USE_PLL_MSK BIT(28)
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#define LNaTGCR0_N_RATE_FULL 0x0
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#define LNaTGCR0_N_RATE_HALF 0x1000000
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#define LNaTGCR0_N_RATE_QUARTER 0x2000000
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#define LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
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#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
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/* Lane a Rx Reset Control Register */
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#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
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#define LYNX_28G_LNaRRSTCTL_HLT_REQ BIT(27)
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#define LYNX_28G_LNaRRSTCTL_RST_DONE BIT(30)
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#define LYNX_28G_LNaRRSTCTL_RST_REQ BIT(31)
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#define LYNX_28G_LNaRRSTCTL_CDR_LOCK BIT(12)
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#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
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#define LNaRRSTCTL_HLT_REQ BIT(27)
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#define LNaRRSTCTL_RST_DONE BIT(30)
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#define LNaRRSTCTL_RST_REQ BIT(31)
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#define LNaRRSTCTL_CDR_LOCK BIT(12)
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/* Lane a Rx General Control Register */
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#define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
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#define LYNX_28G_LNaRGCR0_USE_PLLF 0x0
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#define LYNX_28G_LNaRGCR0_USE_PLLS BIT(28)
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#define LYNX_28G_LNaRGCR0_USE_PLL_MSK BIT(28)
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#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0
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#define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000
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#define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
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#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
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#define LNaRGCR0_USE_PLLF 0x0
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#define LNaRGCR0_USE_PLLS BIT(28)
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#define LNaRGCR0_USE_PLL_MSK BIT(28)
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#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LNaRGCR0_N_RATE_FULL 0x0
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#define LNaRGCR0_N_RATE_HALF 0x1000000
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#define LNaRGCR0_N_RATE_QUARTER 0x2000000
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#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
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#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
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#define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
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#define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
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#define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
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#define LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
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#define LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
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#define LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
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#define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
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#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
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#define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4)
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#define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
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#define LYNX_28G_LNaPSS_TYPE_SGMII 0x4
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#define LYNX_28G_LNaPSS_TYPE_XFI 0x28
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#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
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#define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
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#define LNaPSS_TYPE_SGMII 0x4
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#define LNaPSS_TYPE_XFI 0x28
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#define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
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#define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11)
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#define LYNX_28G_SGMIIaCR1_SGPCS_DIS 0x0
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#define LYNX_28G_SGMIIaCR1_SGPCS_MSK BIT(11)
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#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
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#define SGMIIaCR1_SGPCS_EN BIT(11)
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#define SGMIIaCR1_SGPCS_DIS 0x0
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#define SGMIIaCR1_SGPCS_MSK BIT(11)
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struct lynx_28g_priv;
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@@ -150,19 +150,19 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
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}
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#define lynx_28g_lane_rmw(lane, reg, val, mask) \
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lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
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LYNX_28G_##reg##_##val, LYNX_28G_##reg##_##mask)
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lynx_28g_rmw((lane)->priv, reg(lane->id), \
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reg##_##val, reg##_##mask)
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#define lynx_28g_lane_read(lane, reg) \
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ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
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ioread32((lane)->priv->base + reg((lane)->id))
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#define lynx_28g_pll_read(pll, reg) \
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ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
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ioread32((pll)->priv->base + reg((pll)->id))
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static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
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{
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int i;
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for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
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if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl))
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if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
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continue;
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if (test_bit(intf, priv->pll[i].supported))
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@@ -181,7 +181,7 @@ static struct lynx_28g_pll *lynx_28g_pll_get(struct lynx_28g_priv *priv,
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for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
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pll = &priv->pll[i];
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if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
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if (PLLnRSTCTL_DIS(pll->rstctl))
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continue;
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if (test_bit(intf, pll->supported))
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@@ -199,9 +199,9 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
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struct lynx_28g_pll *pll,
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phy_interface_t intf)
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{
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switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
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case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
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case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
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switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
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case PLLnCR1_FRATE_5G_10GVCO:
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case PLLnCR1_FRATE_5G_25GVCO:
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switch (intf) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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@@ -212,7 +212,7 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
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break;
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}
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break;
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case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
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case PLLnCR1_FRATE_10G_20GVCO:
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switch (intf) {
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_USXGMII:
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@@ -242,20 +242,20 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
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static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
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{
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u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
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struct lynx_28g_priv *priv = lane->priv;
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u32 lane_offset = LNa_PCC_OFFSET(lane);
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/* Cleanup the protocol configuration registers of the current protocol */
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switch (lane->interface) {
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case PHY_INTERFACE_MODE_10GBASER:
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lynx_28g_rmw(priv, LYNX_28G_PCCC,
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LYNX_28G_PCCC_SXGMII_DIS << lane_offset,
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lynx_28g_rmw(priv, PCCC,
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PCCC_SXGMII_DIS << lane_offset,
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GENMASK(3, 0) << lane_offset);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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lynx_28g_rmw(priv, LYNX_28G_PCC8,
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LYNX_28G_PCC8_SGMII_DIS << lane_offset,
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lynx_28g_rmw(priv, PCC8,
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PCC8_SGMII_DIS << lane_offset,
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GENMASK(3, 0) << lane_offset);
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break;
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default:
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@@ -265,15 +265,15 @@ static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
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static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
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{
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u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
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u32 lane_offset = LNa_PCC_OFFSET(lane);
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struct lynx_28g_priv *priv = lane->priv;
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struct lynx_28g_pll *pll;
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lynx_28g_cleanup_lane(lane);
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/* Setup the lane to run in SGMII */
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lynx_28g_rmw(priv, LYNX_28G_PCC8,
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LYNX_28G_PCC8_SGMII << lane_offset,
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lynx_28g_rmw(priv, PCC8,
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PCC8_SGMII << lane_offset,
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GENMASK(3, 0) << lane_offset);
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/* Setup the protocol select and SerDes parallel interface width */
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@@ -295,25 +295,25 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
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lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
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/* Configure the appropriate equalization parameters for the protocol */
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iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));
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iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
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iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));
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iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
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iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));
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iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
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iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
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iowrite32(0x04310000, priv->base + LNaRGCR1(lane->id));
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iowrite32(0x9f800000, priv->base + LNaRECR0(lane->id));
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iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
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iowrite32(0x00000000, priv->base + LNaRECR2(lane->id));
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iowrite32(0x00000000, priv->base + LNaRSCCR0(lane->id));
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}
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static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
|
||||
{
|
||||
u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
|
||||
struct lynx_28g_priv *priv = lane->priv;
|
||||
u32 lane_offset = LNa_PCC_OFFSET(lane);
|
||||
struct lynx_28g_pll *pll;
|
||||
|
||||
lynx_28g_cleanup_lane(lane);
|
||||
|
||||
/* Enable the SXGMII lane */
|
||||
lynx_28g_rmw(priv, LYNX_28G_PCCC,
|
||||
LYNX_28G_PCCC_10GBASER << lane_offset,
|
||||
lynx_28g_rmw(priv, PCCC,
|
||||
PCCC_10GBASER << lane_offset,
|
||||
GENMASK(3, 0) << lane_offset);
|
||||
|
||||
/* Setup the protocol select and SerDes parallel interface width */
|
||||
@@ -335,12 +335,12 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
|
||||
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
|
||||
|
||||
/* Configure the appropriate equalization parameters for the protocol */
|
||||
iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));
|
||||
iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
|
||||
iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));
|
||||
iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
|
||||
iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));
|
||||
iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
|
||||
iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
|
||||
iowrite32(0x10000000, priv->base + LNaRGCR1(lane->id));
|
||||
iowrite32(0x00000000, priv->base + LNaRECR0(lane->id));
|
||||
iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
|
||||
iowrite32(0x81000020, priv->base + LNaRECR2(lane->id));
|
||||
iowrite32(0x00002000, priv->base + LNaRSCCR0(lane->id));
|
||||
}
|
||||
|
||||
static int lynx_28g_power_off(struct phy *phy)
|
||||
@@ -359,8 +359,8 @@ static int lynx_28g_power_off(struct phy *phy)
|
||||
do {
|
||||
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
|
||||
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
|
||||
} while ((trstctl & LYNX_28G_LNaTRSTCTL_HLT_REQ) ||
|
||||
(rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ));
|
||||
} while ((trstctl & LNaTRSTCTL_HLT_REQ) ||
|
||||
(rrstctl & LNaRRSTCTL_HLT_REQ));
|
||||
|
||||
lane->powered_up = false;
|
||||
|
||||
@@ -383,8 +383,8 @@ static int lynx_28g_power_on(struct phy *phy)
|
||||
do {
|
||||
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
|
||||
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
|
||||
} while (!(trstctl & LYNX_28G_LNaTRSTCTL_RST_DONE) ||
|
||||
!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
|
||||
} while (!(trstctl & LNaTRSTCTL_RST_DONE) ||
|
||||
!(rrstctl & LNaRRSTCTL_RST_DONE));
|
||||
|
||||
lane->powered_up = true;
|
||||
|
||||
@@ -495,17 +495,17 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
|
||||
pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0);
|
||||
pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1);
|
||||
|
||||
if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
|
||||
if (PLLnRSTCTL_DIS(pll->rstctl))
|
||||
continue;
|
||||
|
||||
switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
|
||||
case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
|
||||
case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
|
||||
switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
|
||||
case PLLnCR1_FRATE_5G_10GVCO:
|
||||
case PLLnCR1_FRATE_5G_25GVCO:
|
||||
/* 5GHz clock net */
|
||||
__set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
|
||||
__set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
|
||||
break;
|
||||
case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
|
||||
case PLLnCR1_FRATE_10G_20GVCO:
|
||||
/* 10.3125GHz clock net */
|
||||
__set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
|
||||
break;
|
||||
@@ -536,11 +536,11 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
|
||||
}
|
||||
|
||||
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
|
||||
if (!(rrstctl & LYNX_28G_LNaRRSTCTL_CDR_LOCK)) {
|
||||
if (!(rrstctl & LNaRRSTCTL_CDR_LOCK)) {
|
||||
lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
|
||||
do {
|
||||
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
|
||||
} while (!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
|
||||
} while (!(rrstctl & LNaRRSTCTL_RST_DONE));
|
||||
}
|
||||
|
||||
mutex_unlock(&lane->phy->mutex);
|
||||
@@ -554,12 +554,12 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
|
||||
u32 pss, protocol;
|
||||
|
||||
pss = lynx_28g_lane_read(lane, LNaPSS);
|
||||
protocol = LYNX_28G_LNaPSS_TYPE(pss);
|
||||
protocol = LNaPSS_TYPE(pss);
|
||||
switch (protocol) {
|
||||
case LYNX_28G_LNaPSS_TYPE_SGMII:
|
||||
case LNaPSS_TYPE_SGMII:
|
||||
lane->interface = PHY_INTERFACE_MODE_SGMII;
|
||||
break;
|
||||
case LYNX_28G_LNaPSS_TYPE_XFI:
|
||||
case LNaPSS_TYPE_XFI:
|
||||
lane->interface = PHY_INTERFACE_MODE_10GBASER;
|
||||
break;
|
||||
default:
|
||||
|
||||
Reference in New Issue
Block a user