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Merge tag 'irq-urgent-2022-04-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
"A set of interrupt chip driver fixes:
- A fix for a long standing bug in the ARM GICv3 redistributor
polling which uses the wrong bit number to test.
- Prevent translation of bogus ACPI table entries which map device
interrupts into the IPI space on ARM GICs.
- Don't write into the pending register of ARM GICV4 before the scan
in hardware has completed.
- A set of build and correctness fixes for the Qualcomm MPM driver"
* tag 'irq-urgent-2022-04-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic, gic-v3: Prevent GSI to SGI translations
irqchip/gic-v3: Fix GICR_CTLR.RWP polling
irqchip/gic-v4: Wait for GICR_VPENDBASER.Dirty to clear before descheduling
irqchip/irq-qcom-mpm: fix return value check in qcom_mpm_init()
irq/qcom-mpm: Fix build error without MAILBOX
This commit is contained in:
@@ -433,6 +433,7 @@ config QCOM_PDC
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config QCOM_MPM
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tristate "QCOM MPM"
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depends on ARCH_QCOM
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depends on MAILBOX
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select IRQ_DOMAIN_HIERARCHY
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help
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MSM Power Manager driver to manage and configure wakeup
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@@ -3011,18 +3011,12 @@ static int __init allocate_lpi_tables(void)
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return 0;
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}
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static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
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static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
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{
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u32 count = 1000000; /* 1s! */
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bool clean;
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u64 val;
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val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
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val &= ~GICR_VPENDBASER_Valid;
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val &= ~clr;
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val |= set;
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gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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do {
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val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
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clean = !(val & GICR_VPENDBASER_Dirty);
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@@ -3033,10 +3027,26 @@ static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
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}
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} while (!clean && count);
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if (unlikely(val & GICR_VPENDBASER_Dirty)) {
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if (unlikely(!clean))
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pr_err_ratelimited("ITS virtual pending table not cleaning\n");
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return val;
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}
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static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
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{
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u64 val;
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/* Make sure we wait until the RD is done with the initial scan */
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val = read_vpend_dirty_clear(vlpi_base);
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val &= ~GICR_VPENDBASER_Valid;
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val &= ~clr;
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val |= set;
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gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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val = read_vpend_dirty_clear(vlpi_base);
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if (unlikely(val & GICR_VPENDBASER_Dirty))
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val |= GICR_VPENDBASER_PendingLast;
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}
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return val;
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}
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@@ -206,11 +206,11 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
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}
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}
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static void gic_do_wait_for_rwp(void __iomem *base)
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static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
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{
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u32 count = 1000000; /* 1s! */
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while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
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while (readl_relaxed(base + GICD_CTLR) & bit) {
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count--;
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if (!count) {
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pr_err_ratelimited("RWP timeout, gone fishing\n");
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@@ -224,13 +224,13 @@ static void gic_do_wait_for_rwp(void __iomem *base)
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/* Wait for completion of a distributor change */
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static void gic_dist_wait_for_rwp(void)
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{
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gic_do_wait_for_rwp(gic_data.dist_base);
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gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
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}
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/* Wait for completion of a redistributor change */
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static void gic_redist_wait_for_rwp(void)
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{
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gic_do_wait_for_rwp(gic_data_rdist_rd_base());
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gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
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}
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#ifdef CONFIG_ARM64
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@@ -1466,6 +1466,12 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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if(fwspec->param_count != 2)
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return -EINVAL;
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if (fwspec->param[0] < 16) {
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pr_err(FW_BUG "Illegal GSI%d translation request\n",
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fwspec->param[0]);
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return -EINVAL;
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}
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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@@ -1123,6 +1123,12 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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if(fwspec->param_count != 2)
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return -EINVAL;
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if (fwspec->param[0] < 16) {
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pr_err(FW_BUG "Illegal GSI%d translation request\n",
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fwspec->param[0]);
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return -EINVAL;
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}
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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@@ -375,7 +375,7 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
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raw_spin_lock_init(&priv->lock);
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (!priv->base)
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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for (i = 0; i < priv->reg_stride; i++) {
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