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net: stmmac: mdio: move stmmac_mdio_format_addr() into read/write
Move stmmac_mdio_format_addr() into stmmac_mdio_read() and stmmac_mdio_write(). Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Mohd Ayaan Anwar <quic_mohdayaa@quicinc.com> Link: https://patch.msgid.link/E1uu8o7-00000001vom-1pN8@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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committed by
Jakub Kicinski
parent
6717746f33
commit
6cb3d67ad6
@@ -240,16 +240,20 @@ static u32 stmmac_mdio_format_addr(struct stmmac_priv *priv,
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MII_BUSY;
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}
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static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value)
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static int stmmac_mdio_read(struct stmmac_priv *priv, unsigned int pa,
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unsigned int gr, u32 cmd, int data)
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{
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 value;
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int ret;
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ret = stmmac_mdio_wait(priv->ioaddr + mii_address, MII_BUSY);
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if (ret)
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return ret;
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value = stmmac_mdio_format_addr(priv, pa, gr) | cmd;
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writel(data, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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@@ -275,17 +279,18 @@ static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg)
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{
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struct stmmac_priv *priv = netdev_priv(bus->priv);
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int data = 0;
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u32 value;
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u32 cmd;
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data = pm_runtime_resume_and_get(priv->device);
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if (data < 0)
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return data;
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value = stmmac_mdio_format_addr(priv, phyaddr, phyreg);
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if (priv->plat->has_gmac4)
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value |= MII_GMAC4_READ;
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cmd = MII_GMAC4_READ;
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else
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cmd = 0;
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data = stmmac_mdio_read(priv, data, value);
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data = stmmac_mdio_read(priv, phyaddr, phyreg, cmd, data);
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pm_runtime_put(priv->device);
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@@ -308,29 +313,29 @@ static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad,
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{
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struct stmmac_priv *priv = netdev_priv(bus->priv);
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int data = 0;
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u32 value;
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u32 cmd;
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data = pm_runtime_resume_and_get(priv->device);
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if (data < 0)
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return data;
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value = stmmac_mdio_format_addr(priv, phyaddr, devad);
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value |= MII_GMAC4_READ;
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value |= MII_GMAC4_C45E;
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cmd = MII_GMAC4_READ | MII_GMAC4_C45E;
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data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
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data = stmmac_mdio_read(priv, data, value);
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data = stmmac_mdio_read(priv, phyaddr, devad, cmd, data);
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pm_runtime_put(priv->device);
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return data;
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}
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static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value)
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static int stmmac_mdio_write(struct stmmac_priv *priv, unsigned int pa,
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unsigned int gr, u32 cmd, int data)
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{
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 value;
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int ret;
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/* Wait until any existing MII operation is complete */
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@@ -338,6 +343,8 @@ static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value)
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if (ret)
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return ret;
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value = stmmac_mdio_format_addr(priv, pa, gr) | cmd;
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/* Set the MII address register to write */
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writel(data, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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@@ -359,19 +366,18 @@ static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg,
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{
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struct stmmac_priv *priv = netdev_priv(bus->priv);
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int ret, data = phydata;
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u32 value;
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u32 cmd;
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ret = pm_runtime_resume_and_get(priv->device);
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if (ret < 0)
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return ret;
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value = stmmac_mdio_format_addr(priv, phyaddr, phyreg);
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if (priv->plat->has_gmac4)
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value |= MII_GMAC4_WRITE;
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cmd = MII_GMAC4_WRITE;
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else
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value |= MII_WRITE;
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cmd = MII_WRITE;
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ret = stmmac_mdio_write(priv, data, value);
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ret = stmmac_mdio_write(priv, phyaddr, phyreg, cmd, data);
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pm_runtime_put(priv->device);
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@@ -392,19 +398,17 @@ static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr,
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{
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struct stmmac_priv *priv = netdev_priv(bus->priv);
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int ret, data = phydata;
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u32 value;
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u32 cmd;
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ret = pm_runtime_resume_and_get(priv->device);
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if (ret < 0)
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return ret;
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value = stmmac_mdio_format_addr(priv, phyaddr, devad);
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value |= MII_GMAC4_WRITE;
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value |= MII_GMAC4_C45E;
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cmd = MII_GMAC4_WRITE | MII_GMAC4_C45E;
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data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
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ret = stmmac_mdio_write(priv, data, value);
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ret = stmmac_mdio_write(priv, phyaddr, devad, cmd, data);
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pm_runtime_put(priv->device);
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