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Merge tag 'soc-arm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC ARM code updates from Arnd Bergmann: "These are again very minimal updates: - A workaround for firmware on Google Nexus 10 - A fix for early debugging on OMAP1 - A rework for Microchip SoC configuration - Cleanups on OMAP2 an R-Car-Gen2" * tag 'soc-arm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: omap2: dead code cleanup in kconfig for ARCH_OMAP4 ARM: OMAP1: Fix DEBUG_LL and earlyprintk on OMAP16XX arm64: Kconfig: provide a top-level switch for Microchip platforms ARM: shmobile: rcar-gen2: Use of_phandle_args_equal() helper ARM: omap: fix all kernel-doc warnings ARM: omap2: Replace scnprintf with strscpy in omap3_cpuinfo ARM: samsung: exynos5250: Allow CPU1 to boot
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@@ -61,10 +61,10 @@ static int exynos_cpu_boot(int cpu)
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* Exynos3250 doesn't need to send smc command for secondary CPU boot
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* because Exynos3250 removes WFE in secure mode.
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*
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* On Exynos5 devices the call is ignored by trustzone firmware.
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* On most Exynos5 devices the call is ignored by trustzone firmware.
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*/
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if (!soc_is_exynos4210() && !soc_is_exynos4212() &&
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!soc_is_exynos4412())
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!soc_is_exynos4412() && !of_machine_is_compatible("google,manta"))
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return 0;
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/*
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@@ -700,8 +700,8 @@ int __init omap1_clk_init(void)
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/* Make sure UART clocks are enabled early */
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if (cpu_is_omap16xx())
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omap_writel(omap_readl(MOD_CONF_CTRL_0) |
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CONF_MOD_UART1_CLK_MODE_R |
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CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
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(1 << CONF_MOD_UART1_CLK_MODE_R) |
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(1 << CONF_MOD_UART3_CLK_MODE_R), MOD_CONF_CTRL_0);
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#endif
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/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
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@@ -42,7 +42,6 @@ config ARCH_OMAP4
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select PM if CPU_IDLE
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select OMAP_INTERCONNECT
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config SOC_OMAP5
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bool "TI OMAP5"
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@@ -17,6 +17,7 @@
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#include <linux/io.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#ifdef CONFIG_SOC_BUS
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#include <linux/sys_soc.h>
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@@ -250,7 +251,7 @@ static void __init omap3_cpuinfo(void)
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cpu_name = "OMAP3503";
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}
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scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
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strscpy(soc_name, cpu_name);
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/* Print verbose information */
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n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
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@@ -141,7 +141,7 @@ static struct notifier_block regulator_quirk_nb = {
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static int __init rcar_gen2_regulator_quirk(void)
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{
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struct regulator_quirk *quirk, *pos, *tmp;
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struct of_phandle_args *argsa, *argsb;
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struct of_phandle_args *args;
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const struct of_device_id *id;
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struct device_node *np;
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u32 mon, addr;
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@@ -171,14 +171,14 @@ static int __init rcar_gen2_regulator_quirk(void)
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goto err_mem;
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}
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argsa = &quirk->irq_args;
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args = &quirk->irq_args;
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memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
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quirk->id = id;
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quirk->np = of_node_get(np);
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quirk->i2c_msg.addr = addr;
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ret = of_irq_parse_one(np, 0, argsa);
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ret = of_irq_parse_one(np, 0, args);
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if (ret) { /* Skip invalid entry and continue */
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of_node_put(np);
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kfree(quirk);
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@@ -186,15 +186,7 @@ static int __init rcar_gen2_regulator_quirk(void)
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}
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list_for_each_entry(pos, &quirk_list, list) {
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argsb = &pos->irq_args;
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if (argsa->args_count != argsb->args_count)
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continue;
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ret = memcmp(argsa->args, argsb->args,
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argsa->args_count *
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sizeof(argsa->args[0]));
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if (!ret) {
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if (of_phandle_args_equal(args, &pos->irq_args)) {
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pos->shared = true;
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quirk->shared = true;
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}
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@@ -188,16 +188,15 @@ config ARCH_MESON
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This enables support for the arm64 based Amlogic SoCs
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such as the s905, S905X/D, S912, A113X/D or S905X/D2
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menu "Microchip SoC support"
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menuconfig ARCH_MICROCHIP
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bool "Microchip SoC support"
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config ARCH_MICROCHIP
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bool
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if ARCH_MICROCHIP
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config ARCH_LAN969X
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bool "Microchip LAN969X SoC family"
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select PINCTRL
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select DW_APB_TIMER_OF
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select ARCH_MICROCHIP
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help
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This enables support for the Microchip LAN969X ARMv8-based
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SoC family of TSN-capable gigabit switches.
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@@ -212,7 +211,6 @@ config ARCH_SPARX5
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bool "Microchip Sparx5 SoC family"
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select PINCTRL
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select DW_APB_TIMER_OF
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select ARCH_MICROCHIP
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help
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This enables support for the Microchip Sparx5 ARMv8-based
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SoC family of TSN-capable gigabit switches.
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@@ -223,7 +221,7 @@ config ARCH_SPARX5
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security through TCAM-based frame processing using versatile
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content aware processor (VCAP).
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endmenu
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endif
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config ARCH_MMP
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bool "Marvell MMP SoC Family"
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@@ -57,6 +57,7 @@ CONFIG_ARCH_HISI=y
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CONFIG_ARCH_KEEMBAY=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_ARCH_MESON=y
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CONFIG_ARCH_MICROCHIP=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_ARCH_NXP=y
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CONFIG_ARCH_LAYERSCAPE=y
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@@ -10,14 +10,14 @@
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/**
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* struct omap_volt_data - Omap voltage specific data.
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* @voltage_nominal: The possible voltage value in uV
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* @volt_nominal: The possible voltage value in uV
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* @sr_efuse_offs: The offset of the efuse register(from system
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* control module base address) from where to read
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* the n-target value for the smartreflex module.
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* @sr_errminlimit: Error min limit value for smartreflex. This value
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* differs at differnet opp and thus is linked
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* with voltage.
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* @vp_errorgain: Error gain value for the voltage processor. This
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* @vp_errgain: Error gain value for the voltage processor. This
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* field also differs according to the voltage/opp.
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*/
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struct omap_volt_data {
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