Merge tag 'soc-arm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC ARM code updates from Arnd Bergmann:
 "These are again very minimal updates:

   - A workaround for firmware on Google Nexus 10

   - A fix for early debugging on OMAP1

   - A rework for Microchip SoC configuration

   - Cleanups on OMAP2 an R-Car-Gen2"

* tag 'soc-arm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: omap2: dead code cleanup in kconfig for ARCH_OMAP4
  ARM: OMAP1: Fix DEBUG_LL and earlyprintk on OMAP16XX
  arm64: Kconfig: provide a top-level switch for Microchip platforms
  ARM: shmobile: rcar-gen2: Use of_phandle_args_equal() helper
  ARM: omap: fix all kernel-doc warnings
  ARM: omap2: Replace scnprintf with strscpy in omap3_cpuinfo
  ARM: samsung: exynos5250: Allow CPU1 to boot
This commit is contained in:
Linus Torvalds
2026-04-16 20:45:14 -07:00
8 changed files with 17 additions and 26 deletions

View File

@@ -61,10 +61,10 @@ static int exynos_cpu_boot(int cpu)
* Exynos3250 doesn't need to send smc command for secondary CPU boot
* because Exynos3250 removes WFE in secure mode.
*
* On Exynos5 devices the call is ignored by trustzone firmware.
* On most Exynos5 devices the call is ignored by trustzone firmware.
*/
if (!soc_is_exynos4210() && !soc_is_exynos4212() &&
!soc_is_exynos4412())
!soc_is_exynos4412() && !of_machine_is_compatible("google,manta"))
return 0;
/*

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@@ -700,8 +700,8 @@ int __init omap1_clk_init(void)
/* Make sure UART clocks are enabled early */
if (cpu_is_omap16xx())
omap_writel(omap_readl(MOD_CONF_CTRL_0) |
CONF_MOD_UART1_CLK_MODE_R |
CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
(1 << CONF_MOD_UART1_CLK_MODE_R) |
(1 << CONF_MOD_UART3_CLK_MODE_R), MOD_CONF_CTRL_0);
#endif
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */

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@@ -42,7 +42,6 @@ config ARCH_OMAP4
select PM if CPU_IDLE
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select OMAP_INTERCONNECT
config SOC_OMAP5
bool "TI OMAP5"

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@@ -17,6 +17,7 @@
#include <linux/io.h>
#include <linux/random.h>
#include <linux/slab.h>
#include <linux/string.h>
#ifdef CONFIG_SOC_BUS
#include <linux/sys_soc.h>
@@ -250,7 +251,7 @@ static void __init omap3_cpuinfo(void)
cpu_name = "OMAP3503";
}
scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
strscpy(soc_name, cpu_name);
/* Print verbose information */
n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);

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@@ -141,7 +141,7 @@ static struct notifier_block regulator_quirk_nb = {
static int __init rcar_gen2_regulator_quirk(void)
{
struct regulator_quirk *quirk, *pos, *tmp;
struct of_phandle_args *argsa, *argsb;
struct of_phandle_args *args;
const struct of_device_id *id;
struct device_node *np;
u32 mon, addr;
@@ -171,14 +171,14 @@ static int __init rcar_gen2_regulator_quirk(void)
goto err_mem;
}
argsa = &quirk->irq_args;
args = &quirk->irq_args;
memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
quirk->id = id;
quirk->np = of_node_get(np);
quirk->i2c_msg.addr = addr;
ret = of_irq_parse_one(np, 0, argsa);
ret = of_irq_parse_one(np, 0, args);
if (ret) { /* Skip invalid entry and continue */
of_node_put(np);
kfree(quirk);
@@ -186,15 +186,7 @@ static int __init rcar_gen2_regulator_quirk(void)
}
list_for_each_entry(pos, &quirk_list, list) {
argsb = &pos->irq_args;
if (argsa->args_count != argsb->args_count)
continue;
ret = memcmp(argsa->args, argsb->args,
argsa->args_count *
sizeof(argsa->args[0]));
if (!ret) {
if (of_phandle_args_equal(args, &pos->irq_args)) {
pos->shared = true;
quirk->shared = true;
}

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@@ -188,16 +188,15 @@ config ARCH_MESON
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
menu "Microchip SoC support"
menuconfig ARCH_MICROCHIP
bool "Microchip SoC support"
config ARCH_MICROCHIP
bool
if ARCH_MICROCHIP
config ARCH_LAN969X
bool "Microchip LAN969X SoC family"
select PINCTRL
select DW_APB_TIMER_OF
select ARCH_MICROCHIP
help
This enables support for the Microchip LAN969X ARMv8-based
SoC family of TSN-capable gigabit switches.
@@ -212,7 +211,6 @@ config ARCH_SPARX5
bool "Microchip Sparx5 SoC family"
select PINCTRL
select DW_APB_TIMER_OF
select ARCH_MICROCHIP
help
This enables support for the Microchip Sparx5 ARMv8-based
SoC family of TSN-capable gigabit switches.
@@ -223,7 +221,7 @@ config ARCH_SPARX5
security through TCAM-based frame processing using versatile
content aware processor (VCAP).
endmenu
endif
config ARCH_MMP
bool "Marvell MMP SoC Family"

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@@ -57,6 +57,7 @@ CONFIG_ARCH_HISI=y
CONFIG_ARCH_KEEMBAY=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NXP=y
CONFIG_ARCH_LAYERSCAPE=y

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@@ -10,14 +10,14 @@
/**
* struct omap_volt_data - Omap voltage specific data.
* @voltage_nominal: The possible voltage value in uV
* @volt_nominal: The possible voltage value in uV
* @sr_efuse_offs: The offset of the efuse register(from system
* control module base address) from where to read
* the n-target value for the smartreflex module.
* @sr_errminlimit: Error min limit value for smartreflex. This value
* differs at differnet opp and thus is linked
* with voltage.
* @vp_errorgain: Error gain value for the voltage processor. This
* @vp_errgain: Error gain value for the voltage processor. This
* field also differs according to the voltage/opp.
*/
struct omap_volt_data {