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spi: spi_amd: Set controller address mode

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Add changes to set the controller address mode before initiating commands.
The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address
modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit
address mode. So this change is applicable only for SPI0 controller.

Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Raju Rangoju
2024-09-25 19:06:43 +05:30
committed by Mark Brown
parent 145d61c0ab
commit 9674f1694e
1 changed files with 15 additions and 0 deletions
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15
drivers/spi/spi-amd.c
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@@ -34,6 +34,7 @@
#define AMD_SPI_TX_COUNT_REG 0x48
#define AMD_SPI_RX_COUNT_REG 0x4B
#define AMD_SPI_STATUS_REG 0x4C
#define AMD_SPI_ADDR32CTRL_REG 0x50
#define AMD_SPI_FIFO_SIZE 70
#define AMD_SPI_MEM_SIZE 200
@@ -548,6 +549,17 @@ static void amd_spi_mem_data_in(struct amd_spi *amd_spi,
nbytes + i - left_data);
}
static void amd_set_spi_addr_mode(struct amd_spi *amd_spi,
const struct spi_mem_op *op)
{
u32 val = amd_spi_readreg32(amd_spi, AMD_SPI_ADDR32CTRL_REG);
if (amd_is_spi_read_cmd_4b(op->cmd.opcode))
amd_spi_writereg32(amd_spi, AMD_SPI_ADDR32CTRL_REG, val | BIT(0));
else
amd_spi_writereg32(amd_spi, AMD_SPI_ADDR32CTRL_REG, val & ~BIT(0));
}
static int amd_spi_exec_mem_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
@@ -560,6 +572,9 @@ static int amd_spi_exec_mem_op(struct spi_mem *mem,
if (ret)
return ret;
if (amd_spi->version == AMD_SPI_V2)
amd_set_spi_addr_mode(amd_spi, op);
switch (op->data.dir) {
case SPI_MEM_DATA_IN:
amd_spi_mem_data_in(amd_spi, op);