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ALSA: i2c: ak4xxx-adda: seed AK5365 cache with reset defaults
snd_akm4xxx_init() clears the register and volume caches before dispatching by codec type. The AK5365 case then returns immediately, leaving the software cache at zero instead of the documented AK5365 reset defaults. The AK5365 capture volume controls read from volumes[] and the proc register dump reads from images[], so the initial capture volume state and proc output are wrong until a control write happens. Seed the AK5365 cache with its documented reset defaults instead of adding a guessed init sequence. The datasheet documents the reset values and states that MCLK/LRCK changes do not require a PDN/PWN reset because the chip has a built-in reset-free circuit. Signed-off-by: Cássio Gabriel <cassiogabrielcontato@gmail.com> Link: https://patch.msgid.link/20260408-ak5365-cache-defaults-v1-1-fff639aca3e3@gmail.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
committed by
Takashi Iwai
parent
de65275fc9
commit
aa6c1052b7
@@ -281,6 +281,9 @@ void snd_akm4xxx_init(struct snd_akm4xxx *ak)
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0x07, 0x00, /* 7: ROUT muted */
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0xff, 0xff
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};
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static const unsigned char ak5365_defaults[] = {
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0x01, 0x00, 0x00, 0x2b, 0x7f, 0x7f, 0x28, 0x89,
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};
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int chip;
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const unsigned char *ptr, *inits;
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@@ -327,10 +330,12 @@ void snd_akm4xxx_init(struct snd_akm4xxx *ak)
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ak->total_regs = 0x05;
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break;
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case SND_AK5365:
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/* FIXME: any init sequence? */
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ak->num_chips = 1;
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ak->name = "ak5365";
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ak->total_regs = 0x08;
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memcpy(ak->images, ak5365_defaults, sizeof(ak5365_defaults));
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snd_akm4xxx_set_vol(ak, 0, 0x04, 127);
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snd_akm4xxx_set_vol(ak, 0, 0x05, 127);
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return;
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case SND_AK4620:
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inits = inits_ak4620;
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