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Merge tag 'imx-fixes-6.6' into imx/dt64
i.MX fixes for 6.6:
- A couple of i.MX8MP device tree changes from Adam Ford to fix clock
configuration regressions caused by 16c9845248 ("arm64: dts: imx8mp:
don't initialize audio clocks from CCM node").
- Fix pmic-irq-hog GPIO line in imx93-tqma9352 device tree.
- Fix a mmemory leak with error handling path of imx_dsp_setup_channels()
in imx-dsp driver.
- Fix HDMI node in imx8mm-evk device tree.
- Add missing clock enable functionality for imx8mm_soc_uid() function
in soc-imx8m driver.
- Add missing imx8mm-prt8mm.dtb build target.
This commit is contained in:
@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
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@@ -26,7 +26,7 @@
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&adv7533_out>;
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remote-endpoint = <&adv7535_out>;
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};
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};
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};
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@@ -72,6 +72,13 @@
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enable-active-high;
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};
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reg_vddext_3v3: regulator-vddext-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VDDEXT_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000 0>;
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@@ -317,15 +324,16 @@
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hdmi@3d {
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compatible = "adi,adv7535";
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reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
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reg-names = "main", "cec", "edid", "packet";
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reg = <0x3d>;
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interrupt-parent = <&gpio1>;
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interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
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adi,dsi-lanes = <4>;
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adi,input-depth = <8>;
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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adi,input-style = <1>;
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adi,input-justification = "evenly";
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avdd-supply = <&buck5_reg>;
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dvdd-supply = <&buck5_reg>;
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pvdd-supply = <&buck5_reg>;
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a2vdd-supply = <&buck5_reg>;
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v3p3-supply = <®_vddext_3v3>;
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v1p2-supply = <&buck5_reg>;
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ports {
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#address-cells = <1>;
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@@ -334,7 +342,7 @@
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port@0 {
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reg = <0>;
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adv7533_in: endpoint {
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adv7535_in: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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@@ -342,7 +350,7 @@
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port@1 {
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reg = <1>;
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adv7533_out: endpoint {
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adv7535_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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@@ -448,7 +456,7 @@
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reg = <1>;
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dsi_out: endpoint {
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remote-endpoint = <&adv7533_in>;
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remote-endpoint = <&adv7535_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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@@ -381,9 +381,10 @@
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
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assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
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<&clk IMX8MP_AUDIO_PLL2> ;
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assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
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assigned-clock-rates = <12288000>;
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assigned-clock-rates = <12288000>, <361267200>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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@@ -791,6 +791,12 @@
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reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
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clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
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<&clk IMX8MP_CLK_AUDIO_AXI>;
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assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
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<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>,
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<600000000>;
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};
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pgc_gpu2d: power-domain@6 {
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@@ -81,7 +81,7 @@
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&gpio1 {
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pmic-irq-hog {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_LOW>;
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gpios = <3 GPIO_ACTIVE_LOW>;
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input;
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line-name = "PMIC_IRQ#";
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};
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@@ -114,6 +114,7 @@ static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc)
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dsp_chan->idx = i % 2;
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dsp_chan->ch = mbox_request_channel_byname(cl, chan_name);
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if (IS_ERR(dsp_chan->ch)) {
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kfree(dsp_chan->name);
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ret = PTR_ERR(dsp_chan->ch);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Failed to request mbox chan %s ret %d\n",
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@@ -100,6 +100,7 @@ static void __init imx8mm_soc_uid(void)
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{
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void __iomem *ocotp_base;
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struct device_node *np;
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struct clk *clk;
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u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
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IMX8MP_OCOTP_UID_OFFSET : 0;
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@@ -109,11 +110,20 @@ static void __init imx8mm_soc_uid(void)
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ocotp_base = of_iomap(np, 0);
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WARN_ON(!ocotp_base);
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clk = of_clk_get_by_name(np, NULL);
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if (IS_ERR(clk)) {
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WARN_ON(IS_ERR(clk));
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return;
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}
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clk_prepare_enable(clk);
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soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
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soc_uid <<= 32;
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soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
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clk_disable_unprepare(clk);
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clk_put(clk);
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iounmap(ocotp_base);
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of_node_put(np);
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}
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