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Merge tag 'intel-pinctrl-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

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intel-pinctrl for v6.20-1

* Add Nova Lake to the list of supported platforms by platform driver
* Update Kconfig help text to clarify which drivers supports which platforms
* Convert more Intel pin control drivers to use intel_gpio_add_pin_ranges()

Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
2026-01-27 10:53:41 +01:00
parent a4cf8f9722 fc32c5725f
commit ebd2f48dff
3 changed files with 50 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/pinctrl/intel/Kconfig
View File

@@ -45,6 +45,7 @@ config PINCTRL_INTEL_PLATFORM
of Intel PCH pins and using them as GPIOs. Currently the following
Intel SoCs / platforms require this to be functional:
- Lunar Lake
- Nova Lake
- Panther Lake
config PINCTRL_ALDERLAKE
@@ -52,7 +53,10 @@ config PINCTRL_ALDERLAKE
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Alder Lake PCH pins and using them as GPIOs.
PCH pins of the following platforms and using them as GPIOs:
- Alder Lake HX, N, and S
- Raptor Lake HX, E, and S
- Twin Lake
config PINCTRL_BROXTON
tristate "Intel Broxton pinctrl and GPIO driver"
@@ -136,15 +140,17 @@ config PINCTRL_METEORLAKE
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Meteor Lake pins and using them as GPIOs.
SoC pins of the following platforms and using them as GPIOs:
- Arrow Lake (all variants)
- Meteor Lake (all variants)
config PINCTRL_METEORPOINT
tristate "Intel Meteor Point pinctrl and GPIO driver"
select PINCTRL_INTEL
help
Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
This pinctrl driver provides an interface that allows configuring
PCH pins of the following platforms and using them as GPIOs:
- Arrow Lake HX and S
config PINCTRL_SUNRISEPOINT
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
@@ -159,7 +165,11 @@ config PINCTRL_TIGERLAKE
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Tiger Lake PCH pins and using them as GPIOs.
PCH pins of the following platforms and using them as GPIOs:
- Alder Lake H, P, PS, and U
- Raptor Lake H, P, PS, PX, and U
- Rocket Lake S
- Tiger Lake (all variants)
source "drivers/pinctrl/intel/Kconfig.tng"
endmenu

41
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@@ -101,10 +101,12 @@ struct intel_pad_context {
u32 val;
};
#define COMMUNITY(p, n, map) \
#define BYT_COMMUNITY(p, n, g, map) \
{ \
.pin_base = (p), \
.npins = (n), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
.pad_map = (map),\
}
@@ -360,8 +362,15 @@ static const struct intel_function byt_score_functions[] = {
FUNCTION("gpio", byt_score_gpio_groups),
};
static const struct intel_padgroup byt_score_gpps[] = {
INTEL_GPP(0, 0, 31, 0),
INTEL_GPP(1, 32, 63, 32),
INTEL_GPP(2, 64, 95, 64),
INTEL_GPP(3, 96, 101, 96),
};
static const struct intel_community byt_score_communities[] = {
COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
BYT_COMMUNITY(0, 102, byt_score_gpps, byt_score_pins_map),
};
static const struct intel_pinctrl_soc_data byt_score_soc_data = {
@@ -483,8 +492,13 @@ static const struct intel_function byt_sus_functions[] = {
FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
};
static const struct intel_padgroup byt_sus_gpps[] = {
INTEL_GPP(0, 0, 31, 0),
INTEL_GPP(1, 32, 43, 32),
};
static const struct intel_community byt_sus_communities[] = {
COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
BYT_COMMUNITY(0, 44, byt_sus_gpps, byt_sus_pins_map),
};
static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
@@ -536,8 +550,12 @@ static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
3, 6, 10, 13, 2, 5, 9, 7,
};
static const struct intel_padgroup byt_ncore_gpps[] = {
INTEL_GPP(0, 0, 27, 0),
};
static const struct intel_community byt_ncore_communities[] = {
COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
BYT_COMMUNITY(0, 28, byt_ncore_gpps, byt_ncore_pins_map),
};
static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
@@ -1490,19 +1508,6 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
return 0;
}
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct intel_pinctrl *vg = gpiochip_get_data(chip);
struct device *dev = vg->dev;
int ret;
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
if (ret)
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
return 0;
}
static int byt_gpio_probe(struct intel_pinctrl *vg)
{
struct platform_device *pdev = to_platform_device(vg->dev);
@@ -1515,7 +1520,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
gc->label = dev_name(vg->dev);
gc->base = -1;
gc->can_sleep = false;
gc->add_pin_ranges = byt_gpio_add_pin_ranges;
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
gc->parent = vg->dev;
gc->ngpio = vg->soc->npins;

27
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@@ -29,10 +29,12 @@
#include "pinctrl-intel.h"
#define COMMUNITY(p, n) \
#define LPTLP_COMMUNITY(p, n, g) \
{ \
.pin_base = (p), \
.npins = (n), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
static const struct pinctrl_pin_desc lptlp_pins[] = {
@@ -133,8 +135,14 @@ static const struct pinctrl_pin_desc lptlp_pins[] = {
PINCTRL_PIN(94, "GP94_UART0_CTSB"),
};
static const struct intel_padgroup lptlp_gpps[] = {
INTEL_GPP(0, 0, 31, 0),
INTEL_GPP(1, 32, 63, 32),
INTEL_GPP(2, 64, 94, 64),
};
static const struct intel_community lptlp_communities[] = {
COMMUNITY(0, 95),
LPTLP_COMMUNITY(0, 95, lptlp_gpps),
};
static const struct intel_pinctrl_soc_data lptlp_soc_data = {
@@ -692,19 +700,6 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
return 0;
}
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
struct device *dev = lg->dev;
int ret;
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
if (ret)
return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
return 0;
}
static int lp_gpio_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc;
@@ -777,7 +772,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
gc->base = -1;
gc->ngpio = LP_NUM_GPIO;
gc->can_sleep = false;
gc->add_pin_ranges = lp_gpio_add_pin_ranges;
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
gc->parent = dev;
/* set up interrupts */