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memory: tegra: Add support for DBB clock on Tegra264

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The DBB clock is needed by many IP blocks in order to access system
memory via the data backbone. The memory controller and external memory
controllers are the central place where these accesses are managed, so
make sure that the clock can be controlled from the corresponding
driver.

Note that not all drivers fully register bandwidth requests, and hence
the EMC driver doesn't have enough information to know when it's safe to
switch the clock off, so for now it will be kept on permanently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260116123732.140813-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Thierry Reding
2026-01-16 13:37:32 +01:00
committed by Krzysztof Kozlowski
parent 6de23f81a5
commit ef4d7b9975
1 changed files with 8 additions and 0 deletions
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8
drivers/memory/tegra/tegra186-emc.c
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@@ -22,6 +22,7 @@ struct tegra186_emc {
struct tegra_bpmp *bpmp;
struct device *dev;
struct clk *clk;
struct clk *clk_dbb;
struct tegra186_emc_dvfs *dvfs;
unsigned int num_dvfs;
@@ -328,6 +329,13 @@ static int tegra186_emc_probe(struct platform_device *pdev)
goto put_bpmp;
}
emc->clk_dbb = devm_clk_get_optional_enabled(&pdev->dev, "dbb");
if (IS_ERR(emc->clk_dbb)) {
err = dev_err_probe(&pdev->dev, PTR_ERR(emc->clk_dbb),
"failed to get DBB clock\n");
goto put_bpmp;
}
platform_set_drvdata(pdev, emc);
emc->dev = &pdev->dev;