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media: staging/ipu7: Update CDPHY register settings

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Some CPHY settings needs to updated according to the latest guide from
SNPS. This patch program 45ohm for tuning resistance to fix CPHY problem
and update the ITMINRX and GMODE for CPHY.

Cc: Stable@vger.kernel.org
Fixes: a516d36bdc ("media: staging/ipu7: add IPU7 input system device driver")
Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Bingbu Cao
2025-12-23 15:23:02 +08:00
committed by Hans Verkuil
parent 1433e6ccc2
commit f7923e6baf
1 changed files with 10 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/staging/media/ipu7/ipu7-isys-csi-phy.c
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@@ -124,6 +124,7 @@ static const struct cdr_fbk_cap_prog_params table7[] = {
{ 1350, 1589, 4 },
{ 1590, 1949, 5 },
{ 1950, 2499, 6 },
{ 2500, 3500, 7 },
{ }
};
@@ -838,9 +839,10 @@ static void ipu7_isys_cphy_config(struct ipu7_isys *isys, u8 id, u8 lanes,
dwc_phy_write_mask(isys, id, reg + 0x400 * i,
reset_thresh, 9, 11);
/* Tuning ITMINRX to 2 for CPHY */
reg = CORE_DIG_CLANE_0_RW_LP_0;
for (i = 0; i < trios; i++)
dwc_phy_write_mask(isys, id, reg + 0x400 * i, 1, 12, 15);
dwc_phy_write_mask(isys, id, reg + 0x400 * i, 2, 12, 15);
reg = CORE_DIG_CLANE_0_RW_LP_2;
for (i = 0; i < trios; i++)
@@ -860,7 +862,11 @@ static void ipu7_isys_cphy_config(struct ipu7_isys *isys, u8 id, u8 lanes,
for (i = 0; i < (lanes + 1); i++) {
reg = CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9 + 0x400 * i;
dwc_phy_write_mask(isys, id, reg, 4U, 0, 2);
dwc_phy_write_mask(isys, id, reg, 0U, 3, 4);
/* Set GMODE to 2 when CPHY >= 1.5Gsps */
if (mbps >= 1500)
dwc_phy_write_mask(isys, id, reg, 2U, 3, 4);
else
dwc_phy_write_mask(isys, id, reg, 0U, 3, 4);
reg = CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7 + 0x400 * i;
dwc_phy_write_mask(isys, id, reg, cap_prog, 10, 12);
@@ -930,8 +936,9 @@ static int ipu7_isys_phy_config(struct ipu7_isys *isys, u8 id, u8 lanes,
7, 12, 14);
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7,
0, 8, 10);
/* resistance tuning: 1 for 45ohm, 0 for 50ohm */
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5,
0, 8, 8);
1, 8, 8);
if (aggregation)
phy_mode = isys->csi2[0].phy_mode;