Add DT compatible for SolidRun Armada-385 based Clearfog GTR L8 and S4
boards.
Despite similar name these two boards are designed differently from the
armada 388 clearfog base and pro, they only share a name and general use
case.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add DT compatible for the helios-4 nas by Kobol, which is already used
in-tree.
This product shares a common system on module with the solidrun armada
388 clearfog boards, however it is not easily described in a single
list due to their extra "solidrun,clearfog-a1" compatible string.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add DT compatible for SolidRun Armada-388 based Clearfog Base and Pro
boards, which are already in place in-tree.
There are already 3 distinct dts in tree for these *two* boards,
declaring particular compatible strings:
the generic "armada-388-clearfog.dts" is a legacy name for the Pro
version, old versions of u-boot built when only one variant existed
explicitly boot by this name.
The other two add explicit -pro / -base suffix to the filename, these
are preferred and chosen by latest u-boot.
Note that both compatibles and model field include the string "A1".
At least up to revision 2.0 of the board, this had been printed
on the pcb. However in marketing material and conversations it is
usually omitted. "Clearfog Pro" and "Clearfog Pro A1" always mean
exactly the same product.
Technically Base and Pro variants are similar enough that they can
successfully boot with each other's dts. Hence it makes (some)
sense for them to share the "clearfog-a1" compatible.
Add bindings for the explicit variants -pro and -base - including a
shared compatible string between the two.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Convert the existing txt binding for armada-38x socs to DT schema
format.
The current bindings documentation for armada-38x are only listing SoCs,
but no actual boards. Only actual boards should be listed.
Replace the dropped entries with some actual baords that already have
valid compatibles in-tree:
- armada 380 netgear switch
- armada 385 marvell development boards
- armada 388 development board
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The unit for TPDM DSB element size is bits. So rename the property:
qcom,dsb-element-size => qcom,dsb-element-bits
This also makes it consistent with the naming for the CMB element
size property.
There is no tpdm node in any DT as of now. Make this change before
any tpdm node is added to DT.
Fixes: 2a8d9b3715 ("dt-bindings: arm: Add support for DSB element size")
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240218094322.22470-2-quic_jinlmao@quicinc.com
[ Reworded commit description to explain why we change this ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Add a new compatible string to support MP25 SoC.
On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM
controller signal) have been integrated together in the SoC. That means
that the NAND controller and the PSRAM controller (if the signal is
used) can not be used at the same time. On MP25 SoC, the 2 signals can
be used outside the SoC, so there is no more restrictions.
MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds
revision 2.0 of the FMC2 IP.
MP25 SoC is also using PSCI OS-initiated mode, so allow a single
'power-domains' entry for STM32 FMC2. As MP1 will move on PSCI
OS-initiated mode, add this property as optional for all FMC2 variants.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Link: https://lore.kernel.org/r/20240226101428.37791-2-christophe.kerello@foss.st.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add initial device tree documentation for Maxim MAX6958/6959.
As per reviewer's request mention the fact of absence the reset
and power enable pins, since the hardware is quite simple.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
i.MX6UL(L) uses "fsl,imx6sx-lcdif" as fallback compatible string,
but has only very lightweight DISPLAY power domain. Its DISPLAY
power domain is not supported by the binding / Linux kernel at
the moment. Since the current setup is working, let's remove the
power-domain from being required for that platform to fix the warning
printed by CHECK_DTBS=y.
Fixes: f62678a77d ("dt-bindings: mxsfb: Document i.MX8M/i.MX6SX/i.MX6SL power-domains property")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20240224213240.1854709-7-sre@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Cadence TTC can act as PWM device, it will be supported through
separate PWM framework based driver. Decision to configure
specific TTC device as PWM or clocksource/clockevent would
be done based on presence of "#pwm-cells" property.
Also, interrupt property is not required for TTC PWM driver.
Update bindings to support TTC PWM configuration.
Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240226093333.2581092-1-mubin.sayyed@amd.com
pinctrl: renesas: Updates for v6.9 (take two)
- Add support for the R-Car V4M (R8A779H0) SoC,
- Add support for suspend/resume on the RZ/G2L family,
- Miscellaneous fixes and improvements.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The minimum number of array entries for "gpios-states" was not not
specified, so the the default is the same as the max (8).
The minimum is also missing from "states", and the maximum is also wrong
as it should be 2^(# of GPIO lines). Since there can be 1 to 8 GPIOs,
the "states" range should be 2 to 256.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://msgid.link/r/20240224000752.3830665-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Add property ti,rmii-mode to support selecting the RMII operation mode
between:
- master mode (PHY operates from a 25MHz clock reference)
- slave mode (PHY operates from a 50MHz clock reference)
If not set, the operation mode is configured by hardware straps.
Signed-off-by: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Thomas Zimmermann asked to backmerge -rc6 for drm-misc branches,
there's a few same-area-changed conflicts (xe and amdgpu mostly) that
are getting a bit too annoying.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
We need it here for the USB fixes, and it resolves a merge conflict as
reported in linux-next in drivers/usb/roles/class.c
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
UBI volumes may be used to contain NVMEM bits, typically device MAC
addresses or wireless radio calibration data.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Richard Weinberger <richard@nod.at>
