Explicit in optee firmware device tree bindings that the interrupt
used by optee driver for async notification can be a peripheral
interrupt or a per-cpu interrupt.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Introduce per-SoC compatibles for OSM targets (read: pre-sm8250) and
sanitize the number of interrupt{s,-names} and reg/-names per-compatible.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
AM62 family of devices don't have a R5F cluster, instead they have
single core DM R5F. Add new compatible string ti,am62-r5fss to support
this scenario.
When this new compatible is used cluster-mode property can only be set
to value 3 i.e. CLUSTER_MODE_SINGLECORE which is also the default value
in case cluster-mode is not defined in device-tree.
While at it, also sort the compatible lists in alphabetical order.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20230327152832.923480-3-devarsht@ti.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
The depth of the FIFO of the Cadence I2C controller IP is a synthesis
configuration parameter. Different instances of the IP can have different
values. For correct operation software needs to be aware of the size of the
FIFO.
Add the documentation for the devicetree property that describes the FIFO
depth of the IP core.
The default value of 16 is for backwards compatibility reasons with
existing hardware descriptions where this property is not specified and
software has assumed that the FIFO depth is 16.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Now we have the i2c-scl-clk-low-timeout-us property defined in
the i2c schema.
Mark "fsl,timeout" as deprecated and update the example.
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
The MT6795 SoC uses the same I2C controller parameters as MT8173:
add a new compatible string for it.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
In the patch ("dt-bindings: pinctrl: qcom: tlmm should use
output-disable, not input-enable") we allowed setting "output-disable"
for TLMM pinctrl states. Let's also add "output-enable".
At first blush this seems a needless thing to do. Specifically:
- In Linux (and presumably any other OSes using the same device trees)
the GPIO/pinctrl driver knows to automatically enable the output
when a GPIO is changed to an output. Thus in most cases specifying
"output-enable" is superfluous and should be avoided.
- If we need to set a pin's default state we already have
"output-high" and "output-low" and these properties already imply
"output-enabled" (at least on the Linux Qualcomm TLMM driver).
However, there is one instance where "output-enable" seems like it
could be useful: sleep states. It's not uncommon to want to configure
pins as inputs (with appropriate pulls) when the driver controlling
them is in a low power state. Then we want the pins back to outputs
when the driver wants things running normally. To accomplish this we'd
want to be able to use "output-enable". Then the "default" state could
have "output-enable" and the "sleep" state could have
"output-disable".
NOTE: in all instances I'm aware of, we'd only want to use
"output-enable" on pins that are configured as "gpio". The Qualcomm
documentation that I have access to says that "output-enable" only
does something useful when in GPIO mode.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230323102605.7.I7874c00092115c45377c2a06f7f133356956686e@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As evidenced by the Qualcomm TLMM Linux driver, the TLMM IP block in
Qualcomm SoCs has a bit to enable/disable the output for a pin that's
configured as a GPIO but _not_ a bit to enable/disable an input
buffer. Current device trees that are specifying "input-enable" for
pins managed by TLMM are either doing so needlessly or are using it to
mean "output-disable".
Presumably the current convention of using "input-enable" to mean
"output-disable" stems from the fact that "output-disable" is a "new"
property from 2017. It was introduced in commit 425562429d
("pinctrl: generic: Add output-enable property"). The "input-enable"
handling in Qualcomm drivers is from 2015 introduced in commit
407f5e392f ("pinctrl: qcom: handle input-enable pinconf property").
Given that there's no other use for "input-enable" for TLMM, we can
still handle old device trees in code, but let's encourage people to
move to the proper / documented property by updating the bindings.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Merge series from Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>:
Hi,
Dependencies
============
For va-macro bindings:
https://lore.kernel.org/r/20221118071849.25506-2-srinivas.kandagatla@linaro.org
NOT a dependency
================
The patchset can be applied independently of my previous fix:
https://lore.kernel.org/linux-arm-msm/20230310100937.32485-1-krzysztof.kozlowski@linaro.org/T/#u
Logically, better if they were together, but code will work fine other way.
Changes since v1
================
1. Move the flag define to common header.
Best regards,
Krzysztof
Krzysztof Kozlowski (9):
ASoC: dt-bindings: qcom,lpass-rx-macro: narrow clocks per variants
ASoC: dt-bindings: qcom,lpass-rx-macro: Add SM8550 RX macro
ASoC: codecs: lpass-rx-macro: add support for SM8550
ASoC: dt-bindings: qcom,lpass-tx-macro: narrow clocks per variants
ASoC: dt-bindings: qcom,lpass-tx-macro: Add SM8550 TX macro
ASoC: codecs: lpass-tx-macro: add support for SM8550
ASoC: dt-bindings: qcom,lpass-va-macro: Add SM8550 VA macro
ASoC: dt-bindings: qcom,lpass-wsa-macro: Add SM8550 WSA macro
ASoC: codecs: lpass-wsa-macro: add support for SM8550
.../bindings/sound/qcom,lpass-rx-macro.yaml | 76 +++++++++++++----
.../bindings/sound/qcom,lpass-tx-macro.yaml | 81 +++++++++++++++----
.../bindings/sound/qcom,lpass-va-macro.yaml | 18 +++++
.../bindings/sound/qcom,lpass-wsa-macro.yaml | 23 +++++-
sound/soc/codecs/lpass-macro-common.h | 3 +
sound/soc/codecs/lpass-rx-macro.c | 36 +++++++--
sound/soc/codecs/lpass-tx-macro.c | 35 ++++++--
sound/soc/codecs/lpass-wsa-macro.c | 37 +++++++--
8 files changed, 252 insertions(+), 57 deletions(-)
--
2.34.1
This adds the following apple,t8112 platforms:
- apple,j413 - MacBook Air (M2, 2022)
- apple,j473 - Mac mini (M2, 2023)
- apple,j493 - MacBook Pro (13-inch, M2, 2022)
The sort order logic here is having SoC numeric code families in release
order, and SoCs within each family in release order:
- t8xxx (Apple HxxP/G series, "phone"/"tablet" chips)
- t8103 (Apple H13G/M1)
- t8112 (Apple H14G/M2)
- t6xxx (Apple HxxJ series, "desktop" chips)
- t6000 (Apple H13J(S)/M1 Pro)
- t6001 (Apple H13J(C)/M1 Max)
- t6002 (Apple H13J(D)/M1 Ultra)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
This block on the Apple M2 is compatible with the existing driver so
just add the per-SoC compatible.
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
