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Author SHA1 Message Date
Luca Weiss
5009024ad7 dt-bindings: clock: qcom: document the Milos TCSR Clock Controller 
Add bindings documentation for the Milos (e.g. SM7635) TCSR Clock
Controller.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-3-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:15:25 -05:00
Luca Weiss
136e6393a5 dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller 
Add bindings documentation for the Milos (e.g. SM7635) RPMH Clock
Controller.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-1-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:15:25 -05:00
Taniya Das
9c51c66c99 dt-bindings: clock: Add Qualcomm QCS615 Video clock controller 
Add DT bindings for the Video clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
3590dfbdd1 dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller 
Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
8b1750ea00 dt-bindings: clock: Add Qualcomm QCS615 Display clock controller 
Add DT bindings for the Display clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
8df2964990 dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller 
Add DT bindings for the Camera clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:05 -05:00
Bjorn Andersson
3c4ee2cc7f Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17 
Merge the IPQ5018 CMN PLL binding through a topic branch, to allow
merging the clock defines into DeviceTree branch as well.
 2025-07-16 23:04:22 -05:00
George Moussalem
314b903c30 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC 
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:03:27 -05:00
Ezra Buehler
292f0b50d3 dt-bindings: clock: mediatek,mtmips-sysc: Adapt compatible for MT7688 boards 
As the MT7628 and MT7688 are identical in most respects, mt7628a.dtsi is
used for both SoCs. To prevent "Kernel panic - not syncing: unable to
get CPU clock, err=-2" and allow an MT7688-based board to boot, the
following must be allowed:

    compatible = "ralink,mt7628-sysc", "ralink,mt7688-sysc", "syscon";

Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
 2025-07-02 13:17:24 +02:00
Julien Massot
a42b4dcc4f dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 
The '#reset-cells' property is permitted for some of the MT8188
clock controllers, but not listed as a valid property.

Fixes: 9a5cd59640 ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-20 18:17:23 -07:00
Frank Li
4c55936671 dt-bindings: clock: convert lpc1850-ccu.txt to yaml format 
Convert lpc1850-ccu.txt to yaml format.

Additional changes:
- remove label in examples.
- remove clock consumer in examples.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250602141937.942091-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-19 13:02:33 -07:00
Geert Uytterhoeven
5701451e84 Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17 
Renesas RZ/N2H DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
SoC, shared by driver and DT source files.
 2025-06-19 20:19:13 +02:00
Lad Prabhakar
292bf6c5b8 dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support 
Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC.  The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-19 20:08:13 +02:00
Rob Herring (Arm)
2e090ae61f dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema 
Convert the Alphascale Clock Controller binding to DT schema format.
Add the undocumented 'clocks' property which is used in DTS. Drop the
clock defines and consumer examples from the old binding.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004712.1793193-1-robh@kernel.org
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:42:10 -07:00
Rob Herring (Arm)
cc33289129 dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema 
Convert the Marvell Armada 3xx Core Divider clock binding to DT schema
format.

Add the missing "marvell,armada-390-corediv-clock" compatible and
"clock-output-names" property.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521211840.77487-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:41:42 -07:00
Rob Herring (Arm)
ed4ce1d924 dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema 
Convert the Marvell Armada 3700 peripheral clock binding to DT schema
format. The north bridge is also a "syscon", so add the compatible to
it.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521211826.77098-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:41:30 -07:00
Rob Herring (Arm)
7cbc8535b2 dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema 
Convert the Marvell SoC core clock binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210844.62613-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:41:24 -07:00
Rob Herring (Arm)
75cc48275f dt-bindings: clock: Convert marvell,berlin2-clk to DT schema 
Convert the Marvell Berlin2 clock binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210839.62409-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:41:02 -07:00
Rob Herring (Arm)
e3fcba910a dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema 
Convert the Marvell Dove PLL divider clock binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210832.62177-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:40:48 -07:00
Rob Herring (Arm)
9919d2a81b dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema 
Convert the Marvell Armada 3700 TBG clock binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210826.61957-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:40:34 -07:00
Rob Herring (Arm)
e9a17eaaf1 dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema 
Convert the Marvell gating clock binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210813.61484-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:40:24 -07:00
Rob Herring (Arm)
12fa3aaf8b dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema 
Convert the Marvell Armada XP CPU clock binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210806.61286-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:40:14 -07:00
Rob Herring (Arm)
f139defc6b dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema 
Convert the TI-NSPIRE clock bindings to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210750.60759-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:40:02 -07:00
Rob Herring (Arm)
bb21488670 dt-bindings: clock: Convert lsi,axm5516-clks to DT schema 
Convert the Intel/LSI AXM5516 clock binding to DT schema format. It's
a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210741.60467-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:39:52 -07:00
Rob Herring (Arm)
46dba2e6a3 dt-bindings: clock: Convert img,pistachio-clk to DT schema 
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

Link: https://lore.kernel.org/r/20250521210712.59742-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:39:41 -07:00
Rob Herring (Arm)
100026f4b5 dt-bindings: clock: Convert brcm,bcm2835-cprman to DT schema 
Convert the Broadcom BCM2835 CPRMAN clock binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004625.1791913-1-robh@kernel.org
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
[sboyd@kernel.org: Add list to maintainers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:38:43 -07:00
Rob Herring (Arm)
add0c5621c dt-bindings: clock: Convert cirrus,ep7209-clk to DT schema 
Convert the Cirrus EP7xxx (aka CLPS711x) binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004923.1795927-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:36:48 -07:00
Rob Herring (Arm)
094e11183d dt-bindings: clock: Convert APM XGene clocks to DT schema 
Convert the APM XGene clocks to DT schema. The device clock binding is
a bit different from the others, so put it in its own schema file.
Drop the examples.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004655.1792703-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:35:16 -07:00
Rob Herring (Arm)
bd6ada566e dt-bindings: clock: Convert axis,artpec6-clkctrl to DT schema 
Convert the Axis ARTPEC-6 clock controller to DT schema format. It's a
straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004647.1792464-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:35:01 -07:00
Rob Herring (Arm)
4a7d79c8b0 dt-bindings: clock: Convert brcm,bcm53573-ilp to DT schema 
Convert the Broadcom BCM53573 ILP clock binding to DT schema format.
It's a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004618.1791669-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-18 18:25:43 -07:00
Bjorn Andersson
c1e21ccfe4 Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17 
Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.
 2025-06-18 17:16:38 -05:00
Luo Jie
0c25ae62f5 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC 
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.

Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-18 17:16:26 -05:00
Raghav Sharma
da5cb65d25 dt-bindings: clock: exynosautov920: add hsi2 clock definitions 
Add device tree clock binding definitions for CMU_HSI2

Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250529112640.1646740-3-raghav.s@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-06-12 17:26:57 +02:00
Raghav Sharma
3d6470990b dt-bindings: clock: exynosautov920: sort clock definitions 
Sort all the clock compatible strings in alphabetical order

Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250529112640.1646740-2-raghav.s@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-06-12 17:26:57 +02:00
Rob Herring (Arm)
554ec5b1bd dt-bindings: clock: Convert brcm,bcm63xx-clocks to DT schema 
Convert the Broadcom BCM63xx clock bindings to DT schema format. It's
a straight forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004610.1791426-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-11 11:21:55 -05:00
Sukrut Bellary
358df002da dt-bindings: clock: ti: add ti,autoidle.yaml reference 
ti,divider-clock uses properties from ti,autoidle.
As we are converting autoidle binding to ti,autoidle.yaml, fix the reference
here.

Signed-off-by: Sukrut Bellary <sbellary@baylibre.com>
Link: https://lore.kernel.org/r/20250516081612.767559-4-sbellary@baylibre.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-11 11:13:16 -05:00
Sukrut Bellary
a7953b62de dt-bindings: clock: ti: Convert fixed-factor-clock to yaml 
This uses the ti,autoidle.yaml for clock autoidle support. Clean up the example
to meet the current standards.

Add the creator of the original binding as a maintainer.

Signed-off-by: Sukrut Bellary <sbellary@baylibre.com>
Link: https://lore.kernel.org/r/20250516081612.767559-3-sbellary@baylibre.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-11 11:13:08 -05:00
Sukrut Bellary
5ffe2d2f53 dt-bindings: clock: ti: Convert autoidle binding to yaml 
Autoidle clock is not an individual clock; it is always a derivate of some
basic clock like a gate, divider, or fixed-factor. This binding will be
referred in ti,divider-clock.yaml, and ti,fixed-factor-clock.yaml.

As all clocks don't support the autoidle feature e.g.,
in DRA77xx/AM57xx[1], dpll_abe_x2* and dpll_per_x2 don't have
autoidle, remove required properties from the binding.

Add the creator of the original binding as a maintainer.

[1] https://www.ti.com/lit/ug/spruhz6l/spruhz6l.pdf

Signed-off-by: Sukrut Bellary <sbellary@baylibre.com>
Link: https://lore.kernel.org/r/20250516081612.767559-2-sbellary@baylibre.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-06-11 11:12:54 -05:00
Bjorn Andersson
910ad0190c Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17 
Merge topic branch with missing GCC clocks and the camera clock
controller for SC8180X through a topic branch, to make it available for
DeviceTree inclusion as well.
 2025-06-10 22:14:41 -05:00
Satya Priya Kakitapalli
b5975ce461 dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller 
Add device tree bindings for the camera clock controller on
Qualcomm SC8180X platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:14:31 -05:00
Jagadeesh Kona
842fa74829 dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc 
SC8280XP camcc only requires the MMCX power domain, unlike SM8450 camcc
which now supports both MMCX and MXC power domains. Hence move SC8280XP
camcc from SM8450 to SA8775P camcc, to have single power domain support.

SA8775P camcc doesn't support required-opps property currently but SC8280XP
camcc need that property,  so add required-opps based on SC8280XP camcc
conditional check in SA8775P camcc bindings.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-3-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00
Vladimir Zapolskiy
a02a8f8cb7 dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains 
To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475,
SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX.
Therefore, update the camcc bindings to include the MXC power domain on
these platforms.

Fixes: 9cbc64745f ("dt-bindings: clock: qcom: Add SM8550 camera clock controller")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00
Jagadeesh Kona
1a42f4d4bb dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain 
To configure the video PLLs and enable the video GDSCs on SM8450,
SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
with MMCX. Therefore, update the videocc bindings to include
the MXC power domain on these platforms.

Fixes: 1e910b2ba0 ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00
Claudiu Beznea
705d9f8f18 Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S" 
This reverts commit f33dca9ed6.

Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain IDs.
Currently, there are no device tree users for #power-domain-cell = <1>.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-9-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:24:17 +02:00
Geert Uytterhoeven
e5e8a9cce5 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17 
Renesas RZ/T2H DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077)
SoC, shared by driver and DT source files.
 2025-06-10 10:23:58 +02:00
Andrea della Porta
7b746d584a dt-bindings: clock: Add RaspberryPi RP1 clock bindings 
Add device tree bindings for the clock generator found in RP1 multi
function device, and relative entries in MAINTAINERS file.

Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
 2025-06-09 10:10:30 -07:00
Linus Torvalds
ec71f661a5 Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 
Pull SoC devicetree updates from Arnd Bergmann:
 "There are 11 newly supported SoCs, but these are all either new
  variants of existing designs, or straight reuses of the existing chip
  in a new package:

   - RK3562 is a new chip based on the old Cortex-A53 core, apparently a
     low-cost version of the Cortex-A55 based RK3568/RK3566.

   - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
     set of on-chip peripherals.

   - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
     family

   - Amlogic S6/S7/S7D

   - Samsung Exynos7870 is an older chip similar to Exynos7885

   - WonderMedia wm8950 is a minor variation on the wm8850 chip

   - Amlogic s805y is almost idential to s805x

   - Allwinner A523 is similar to A527 and T527

   - Qualcomm MSM8926 is a variant of MSM8226

   - Qualcomm Snapdragon X1P42100 is related to R1E80100

  There are also 65 boards, including reference designs for the chips
  above, this includes

   - 12 new boards based on TI K3 series chips, most of them from
     Toradex

   - 10 devices using Rockchips RK35xx and PX30 chips

   - 2 phones and 2 laptops based on Qualcomm Snapdragon designs

   - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses

   - 3 Samsung Galaxy phones based on Exynos7870

   - 5 Allwinner based boards using a variety of ARMv8 chips

   - 9 32-bit machines, each based on a different SoC family

  Aside from the new hardware, there is the usual set of cleanups and
  newly added hardware support on existing machines, for a total of 965
  devicetree changesets"

* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
  MAINTAINERS, mailmap: update Sven Peter's email address
  arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
  arm64: dts: nuvoton: Add pinctrl
  ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
  arm64: dts: blaize-blzp1600: Enable GPIO support
  dt-bindings: clock: socfpga: convert to yaml
  arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3562 pcie unit addresses
  arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
  arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
  arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3576 pcie unit addresses
  arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
  arm64: dts: rockchip: Add missing SFC power-domains to rk3576
  Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
  arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
  arm64: dts: mt6359: Rename RTC node to match binding expectations
  arm64: dts: mt8365-evk: Add goodix touchscreen support
  arm64: dts: mediatek: mt8188: Add missing #reset-cells property
  arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
  ...
 2025-05-31 08:08:56 -07:00
Stephen Boyd
63bfd78aae Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next 
* clk-amlogic:
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc

* clk-allwinner:
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  dt-bindings: allwinner: add H616 DE33 clock binding
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: sunxi: Do not enable by default during compile testing
  clk: sunxi-ng: Do not enable by default during compile testing

* clk-rockchip:
  clk: rockchip: rk3528: add slab.h header include
  clk: rockchip: rk3576: add missing slab.h include
  clk: rockchip: rename gate-grf clk file
  clk: rockchip: rename branch_muxgrf to branch_grf_mux
  clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
  clk: rockchip: rk3036: mark ddrphy as critical
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
  clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
  clk: rockchip: Support MMC clocks in GRF region
  dt-bindings: clock: Add GRF clock definition for RK3528
  clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
  clk: rockchip: introduce GRF gates
  clk: rockchip: introduce auxiliary GRFs
  dt-bindings: clock: rk3576: add IOC gated clocks
  clk: rockchip: rk3568: Add PLL rate for 33.3MHz
  clk: rockchip: Drop empty init callback for rk3588 PLL type
  clk: rockchip: rk3588: Add PLL rate for 1500 MHz

* clk-qcom:
  clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
  clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
  clk: qcom: rpmh: make clkaN optional
  clk: qcom: Add support for Camera Clock Controller on QCS8300
  clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
  dt-bindings: clock: add SM6350 QCOM video clock bindings
  clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: Fix missing error check for dev_pm_domain_attach()
 2025-05-29 00:30:39 -07:00
Stephen Boyd
3e515fc860 Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next 
* clk-socfpga:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables

* clk-sophgo:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

* clk-thead:
  clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
  dt-bindings: clock: thead: Add TH1520 VO clock controller

* clk-samsung:
  clk: samsung: correct clock summary for hsi1 block
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: Use samsung CCF common function
 2025-05-29 00:30:28 -07:00
Stephen Boyd
7459da16c9 Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next 
* clk-bindings:
  dt-bindings: clock: Drop st,stm32h7-rcc.txt
  dt-bindings: clock: convert bcm2835-aux-clock to yaml
  dt-bindings: clock: Drop maxim,max77686.txt
  dt-bindings: clock: convert vf610-clock.txt to yaml format

* clk-renesas: (26 commits)
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  ...

* clk-spacemit:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

* clk-cleanup:
  clk: test: Forward-declare struct of_phandle_args in kunit/clk.h
  clk: davinci: Use of_get_available_child_by_name()
  clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
  clk: bcm: rpi: Drop module alias
  clk: bcm: kona: Remove unused scaled_div_build
 2025-05-29 00:30:17 -07:00