Convert the clock device tree bindings to yaml for the Altera SoCFPGA
Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are
subnodes to Altera SOCFPGA Clock Manager, the yaml was added to
socfpga-clk-manager.yaml.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Add device tree bindings for the TH1520 Video Output (VO) subsystem
clock controller. The VO sub-system manages clock gates for multimedia
components including HDMI, MIPI, and GPU.
Document the VIDEO_PLL requirements for the VO clock controller, which
receives its input from the AP clock controller. The VIDEO_PLL is a
Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz
with maximum FOUTVCO of 2376 MHz.
This binding complements the existing AP sub-system clock controller
which manages CPU, DPU, GMAC and TEE PLLs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
Pull clk updates from Stephen Boyd:
"Here's the pile of clk driver patches. The usual suspects^Wsilicon
vendors are all here, adding new SoC support and fixing existing code.
There are a few patches to the clk framework here as well. They've
been baking in linux-next for weeks so I'm hoping we don't have to
revert them. The disable OF node patch is probably the scariest one
although it seems unlikely that a system would be relying on a driver
_not_ probing because the clk never appeared, but you never know.
Nothing looks out of the ordinary on the driver side but that's
because it's mostly a bunch of data.
Core:
- Use dev_err_probe() in the clk registration path (Peering into the
crystal ball shows many patches that remove printks)
- Check for disabled OF nodes in of_clk_get_hw_from_clkspec()
New Drivers:
- Allwinner A523/T527 clk driver
- Qualcomm IPQ9574 NSS clk driver
- Qualcomm QCS8300 GPU and video clk drivers
- Qualcomm SDM429 RPM clks
- Qualcomm QCM6490 LPASS (low power audio) resets
- Samsung Exynos2200: driver for several clock controllers (Alive,
CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS)
- Samsung Exynos7870: Driver for several clock controllers (Alive,
MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI)
- Rockchip rk3528 and rk3562 clk driver
Updates:
- Various fixes to SoC clk drivers for incorrect data, avoid touching
protected registers, etc.
- Additions for some missing clks in existing SoC clk drivers
- DT schema conversions from text to YAML
- Kconfig cleanups to allow drivers to be compiled on moar
architectures"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
dt-bindings: reset: fix double id on rk3562-cru reset ids
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: davinci: remove support for da830
...
Pull MIPS updates from Thomas Bogendoerfer:
- Add support for multi-cluster configuration
- Add quirks for enabling multi-cluster mode on EyeQ6
- Add DTS clocks for ralink
- Cleanup realtek DTS
- Other cleanups and fixes
* tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits)
MIPS: config: omega2+, vocore2: enable CLK_MTMIPS
arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX
MIPS: cm: Fix warning if MIPS_CM is disabled
MIPS: Fix Macro name
MIPS: ds1287: Match ds1287_set_base_clock() function types
MIPS: cevt-ds1287: Add missing ds1287.h include
MIPS: dec: Declare which_prom() as static
MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy()
mips: dts: ralink: mt7628a: update system controller node and its consumers
mips: dts: ralink: mt7620a: update system controller node and its consumers
mips: dts: ralink: rt3883: update system controller node and its consumers
mips: dts: ralink: rt3050: update system controller node and its consumers
mips: dts: ralink: rt2880: update system controller node and its consumers
dt-bindings: clock: add clock definitions for Ralink SoCs
MIPS: Use arch specific syscall name match function
mips: dts: realtek: Add restart to Cisco SG220-26P
mips: dts: realtek: Add RTL838x SoC peripherals
mips: dts: realtek: Replace uart clock property
mips: dts: realtek: Correct uart interrupt-parent
mips: dts: realtek: Add SoC IRQ node for RTL838x
...
* clk-allwinner:
clk: sunxi-ng: add support for the A523/T527 PRCM CCU
clk: sunxi-ng: a523: add reset lines
clk: sunxi-ng: a523: add bus clock gates
clk: sunxi-ng: a523: remaining mod clocks
clk: sunxi-ng: a523: add USB mod clocks
clk: sunxi-ng: a523: add interface mod clocks
clk: sunxi-ng: a523: add system mod clocks
clk: sunxi-ng: a523: add video mod clocks
clk: sunxi-ng: a523: Add support for bus clocks
clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
clk: sunxi-ng: Add support for update bit
clk: sunxi-ng: mp: provide wrappers for setting feature flags
clk: sunxi-ng: mp: introduce dual-divider clock
clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
clk: sunxi-ng: h616: Add clock/reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
* clk-amlogic:
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
* clk-qcom: (41 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()
clk: qcom: videocc: Constify 'struct qcom_cc_desc'
clk: qcom: gpucc: Constify 'struct qcom_cc_desc'
clk: qcom: dispcc: Constify 'struct qcom_cc_desc'
clk: qcom: camcc: Constify 'struct qcom_cc_desc'
dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
clk: qcom: Add support for Video Clock Controller on QCS8300
clk: qcom: Add support for GPU Clock Controller on QCS8300
...
Samsung DTS ARM64 changes for v6.15
1. Google GS101:
- Disable GSA core pinctrl because its registers are not available for
normal world.
- Add APM (Active Power Management) mailbox and the ACPM firmware nodes.
- Add new boards: Google Pixel 6 Pro (Raven).
- Enable framebuffer and reboot-mode.
2. Exynos990:
- Add PERIS clock controller, MCT timer
3. Exynos8895:
- Define all remaining serial engine (USI) and syscon nodes, add MMC.
- Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte).
4. ExynosAutov920: Add UFS and CPU cache information.
5. Various cleanups.
This includes two topic branches with DT bindings, which might be shared
with other trees depending on needs:
1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller
header constants.
2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines
header constants rework.
* tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits)
arm64: dts: tesla: Change labels to lower-case
arm64: dts: exynos: gs101: Change labels to lower-case
arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
arm64: dts: exynosautov920: add CPU cache information
arm64: dts: exynos: gs101: add ACPM protocol node
arm64: dts: exynos: gs101: add AP to APM mailbox node
arm64: dts: exynos: gs101: add SRAM node
arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
arm64: dts: exynos: gs101: align poweroff writes with downstream
arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes
arm64: dts: exynos8895: Rename PMU nodes to fixup sorting
arm64: dts: exynos8895-dreamlte: enable support for the touchscreen
arm64: dts: exynos8895-dreamlte: enable support for microSD storage
arm64: dts: exynos8895: add a node for mmc
arm64: dts: exynos8895: define all usi nodes
arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1
arm64: dts: exynos990: Rename and sort PMU nodes
arm64: dts: exynos990: Add CMU_PERIS and MCT nodes
dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi
dt-bindings: clock: exynos990: Add CMU_PERIS block
...
Link: https://lore.kernel.org/r/20250309185601.10616-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
New boards: MNT-Reform2 laptop (rk3588), OrangePi5-Ultra (rk3588),
Radxa Rock 4D (rk3576), Firefly ROC-RK3576-PC, Photonicat (rk3568)
New overlays: Video-adapters for Theobroma boards and one adapter used
in hw test scenarios.
Interesting bigger changes contain clock support for rk3528; support for
the hdmi1 controller as well as hdmi-audio support on both controllers on
rk3588; the hdmi-receiver of the rk3588 landed, and rk3576 got basic
graphics support and can now do hdmi output.
Another big block is that we're now doing overlays way better and are
including build-testing for applied overlays to the base dtb - similar
to how other arches already do this.
Of cours a big list of more controllers for rk3576 (nvmem, sfc), rk3588
(rng, spdif, regulator for gpu power-domain) and rk3528 (saradc, pinctrl)
And a huge number of board-level improvements and additions.
* tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (89 commits)
arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D
arm64: dts: rockchip: Add SFC nodes for rk3576
arm64: dts: rockchip: Add maskrom button to Radxa E20C
arm64: dts: rockchip: Add SARADC node for RK3528
arm64: dts: rockchip: Add user button to Radxa E20C
arm64: dts: rockchip: Add leds node to Radxa E20C
arm64: dts: rockchip: Add HDMI support for rock-4d
arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
arm64: dts: rockchip: Enable HDMI receiver on rock-5b
arm64: dts: rockchip: Add device tree support for HDMI RX Controller
arm64: dts: rockchip: Add rk3528 QoS register node
dt-bindings: mfd: syscon: Add rk3528 QoS register compatible
arm64: dts: rockchip: add MNT Reform 2 laptop
dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE)
dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon
dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon
arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10
arm64: dts: rockchip: Enable hdmi display on sige5
arm64: dts: rockchip: Add hdmi for rk3576
arm64: dts: rockchip: Add vop for rk3576
...
Link: https://lore.kernel.org/r/13791512.uLZWGnKmhe@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Convert the TI clkctrl clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
reg property is used mostly with one item, in am3xxx also with
an arbitrary number of items, so divert from the original binding
specifying two (probably meaning one address and one size).
The consumer part of the example is left out because the full consumer
node would be needed.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20250311180215.173634-1-andreas@kemnade.info
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for
the main and the PRCM R-CCU.
The source clock list differs in some annoying details, and folding this
into the existing Allwinner CCU clock binding document gets quite
unwieldy, so create a new document for these CCUs.
Add the new compatible string, along with the required input clock
lists. This conditionally describes the input clock lists, to make
adding support for the other two CCUs easier.
Also add the DT binding headers, listing all the clocks with their ID
numbers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The imx8m-clock.yaml binding covers the clock controller inside all
of the i.MX8M Q/M/N/P SoCs. All of them have in common that they
support two operating modes: nominal and overdrive mode.
While the overdrive mode allows for higher frequencies for many IPs,
the nominal mode needs a lower SoC voltage, thereby reducing
heat generation and power usage.
As increasing clock rates beyond the maximum permitted by the supplied
SoC voltage can lead to difficult to debug issues, device tree consumers
would benefit from knowing what mode is active to enforce the clock rate
limits that come with it.
To facilitate this, extend the clock controller bindings with an
optional fsl,operating-mode property. This intentionally allows the
absence of the property, because there is no default suitable for all
boards:
For i.MX8M Mini and Nano, the kernel SoC DTSIs has assigned-clock-rates
that are all achievable in nominal mode. For i.MX8MP, there are some
rates only validated for overdrive mode.
But even for the i.MX8M Mini/Nano boards, we don't know what rates they
may configure at runtime, so it has not been possible so far to infer from
just the device tree what the mode is.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.kernel.org/r/20250218-imx8m-clk-v4-1-b7697dc2dcd0@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
On the MediaTek platform, some SMI LARBs are directly connected to
the SMI Common, while others are connected to the SMI Sub-Common,
which in turn is connected to the SMI Common. The hardware block
diagram can be described as follows.
SMI-Common(Smart Multimedia Interface Common)
|
+----------------+------------------+
| | |
| | |
| | |
| | |
| | |
larb0 SMI-Sub-Common0 SMI-Sub-Common1
| | | | |
larb1 larb2 larb3 larb7 larb9
For previous discussion on the direction of the code modifications,
please refer to:
https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2=
wXpobDWU1CnvkA@mail.gmail.com/
https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey
hP+KJ5Fasm2rFg@mail.gmail.com/
On the MediaTek MT8188 SoC platform, we encountered power-off failures
and SMI bus hang issues during camera stress tests. The issue arises
because bus glitches are sometimes produced when MTCMOS powers on or
off. While this is fairly normal, the software must handle these
glitches to avoid mistaking them for transaction signals. What's
more, this issue emerged only after the initial upstreaming of this
binding. Without these patches, the SMI becomes unstable during camera
stress tests.
The software solutions can be summarized as follows:
1. Use CLAMP to disable the SMI sub-common port after turning off the
LARB CG and before turning off the LARB MTCMOS.
2. Use CLAMP to disable/enable the SMI sub-common port.
3. Implement an AXI reset for SMI LARBs.
This patch add '#reset-cells' for the clock controller located in image,
camera and IPE subsystems.
Signed-off-by: Friday Yang <friday.yang@mediatek.com>
Link: https://lore.kernel.org/r/20250221075058.14180-2-friday.yang@mediatek.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
on these new introduced constants so consumer nodes can easily use the
correct one in DTS files matching properly what is being used in driver
code (clock IDs are implicitly used there).
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
