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Luca Weiss
b21b5b3ae0 clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe 
Add support to register the rcg dfs in qcom_cc_really_probe(). This
allows users to move the call from the probe function to static
properties.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-1-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:17:04 -05:00
Stephan Gerhold
eb1af6ee48 clk: qcom: gcc-x1e80100: Add missing video resets 
Add the missing video resets that are needed for the iris video codec.
Copied from gcc-sm8550.c.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-5-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:16:15 -05:00
Stephan Gerhold
d0b706509f dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets 
Add the missing video resets that are needed for the iris video codec.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-4-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:16:15 -05:00
Stephan Gerhold
92640a6d4a clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 
X1E80100 videocc is identical to the one in SM8550, aside from slightly
different recommended PLL frequencies. Add the separate frequency tables
for that and apply them if the qcom,x1e80100-videocc compatible is used.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-3-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:16:15 -05:00
Stephan Gerhold
b7b0799f0d clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC 
>From the build perspective, the videocc-sm8550 driver doesn't depend on
having one of the GCC drivers enabled. It builds just fine without the GCC
driver. In practice, it doesn't make much sense to have it enabled without
the GCC driver, but currently this extra dependency is inconsistent with
most of the other VIDEOCC entries in Kconfig. This can easily cause
confusion when you see the VIDEOCC options for some of the SoCs but not for
all of them.

Let's just drop the depends line to allow building the videocc driver
independent of the GCC selection. Compile testing with randconfig will also
benefit from keeping the dependencies minimal.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-2-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:16:15 -05:00
Stephan Gerhold
3b4e2820e1 dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible 
X1E80100 videocc is largely identical to SM8550, but needs slightly
different PLL frequencies. Add a separate qcom,x1e80100-videocc compatible
to the existing schema used for SM8550.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-1-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:16:15 -05:00
Luca Weiss
7181c64fdd clk: qcom: tcsrcc-sm8650: Add support for Milos SoC 
The Milos SoC has a very similar tcsrcc block, only TCSR_UFS_CLKREF_EN
uses different regs, and both TCSR_USB2_CLKREF_EN and
TCSR_USB3_CLKREF_EN are not present.

Modify these resources at probe if we're probing for Milos.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-4-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:15:25 -05:00
Luca Weiss
5009024ad7 dt-bindings: clock: qcom: document the Milos TCSR Clock Controller 
Add bindings documentation for the Milos (e.g. SM7635) TCSR Clock
Controller.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-3-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:15:25 -05:00
Luca Weiss
4901838d2b clk: qcom: rpmh: Add support for RPMH clocks on Milos 
Add support for RPMH clocks on Milos SoCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-2-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:15:25 -05:00
Luca Weiss
136e6393a5 dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller 
Add bindings documentation for the Milos (e.g. SM7635) RPMH Clock
Controller.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-1-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:15:25 -05:00
Brian Masney
ebec04773b clk: qcom: spmi-pmic-div: convert from round_rate() to determine_rate() 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-6-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:57 -05:00
Brian Masney
11add2107c clk: qcom: smd-rpm: convert from round_rate() to determine_rate() 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-5-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:57 -05:00
Brian Masney
2c0dce7392 clk: qcom: rpmh: convert from round_rate() to determine_rate() 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-4-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:56 -05:00
Brian Masney
120c4b7a35 clk: qcom: rpm: convert from round_rate() to determine_rate() 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-3-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:56 -05:00
Brian Masney
3ebefed3d3 clk: qcom: gcc-ipq4019: convert from round_rate() to determine_rate() 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-2-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:56 -05:00
Taniya Das
f6a8abe0cc clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver 
Add support for the video clock controller for video clients to
be able to request for the clocks on QCS615 platform.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-9-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
9c51c66c99 dt-bindings: clock: Add Qualcomm QCS615 Video clock controller 
Add DT bindings for the Video clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
f4b5b40805 clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver 
Add support for the graphics clock controller for graphics clients to
be able to request for the clocks on QCS615 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-7-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
3590dfbdd1 dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller 
Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
9b47105f54 clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver 
Add support for the display clock controller for display clients to
be able to request for the clocks on QCS615 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-5-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
8b1750ea00 dt-bindings: clock: Add Qualcomm QCS615 Display clock controller 
Add DT bindings for the Display clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:06 -05:00
Taniya Das
28bc422939 clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver 
Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on QCS615 platform.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-3-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:05 -05:00
Taniya Das
8df2964990 dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller 
Add DT bindings for the Camera clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:05 -05:00
Taniya Das
48d2c6dec1 clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs 
The alpha PLLs which slew to a new frequency at runtime would require
the PLL to calibrate at the mid point of the VCO. Add the new PLL ops
which can support the slewing of the PLL to a new frequency.

Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-1-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:12:05 -05:00
George Moussalem
f6a4a55ae5 clk: qcom: gcc-ipq5018: fix GE PHY reset 
The MISC reset is supposed to trigger a resets across the MDC, DSP, and
RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
of the reset definition accordingly in the GCC as per the downstream
driver.

Link: 00743c3e82

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:09:46 -05:00
Loic Poulain
9723807046 clk: qcom: gcc-qcm2290: Set HW_CTRL_TRIGGER for video GDSC 
The venus video driver will uses dev_pm_genpd_set_hwmode() API to switch
the video GDSC to HW and SW control modes at runtime. This requires domain
to have the HW_CTRL_TRIGGER flag.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250613102245.782511-1-loic.poulain@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:08:39 -05:00
George Moussalem
25d1263056 clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support 
The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
ethernet block.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-3-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:05:19 -05:00
George Moussalem
693a723291 clk: qcom: ipq5018: keep XO clock always on 
The XO clock must not be disabled to avoid the kernel trying to disable
the it. As such, keep the XO clock always on by flagging it as critical.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-1-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:05:19 -05:00
Bjorn Andersson
3c4ee2cc7f Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17 
Merge the IPQ5018 CMN PLL binding through a topic branch, to allow
merging the clock defines into DeviceTree branch as well.
 2025-07-16 23:04:22 -05:00
George Moussalem
314b903c30 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC 
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-07-16 23:03:27 -05:00
Luo Jie
a2afa4c33f clk: qcom: cmnpll: Add IPQ5424 SoC support 
The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
and their rates are same as IPQ9574.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-2-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-18 17:17:43 -05:00
Bjorn Andersson
c1e21ccfe4 Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17 
Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.
 2025-06-18 17:16:38 -05:00
Luo Jie
0c25ae62f5 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC 
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.

Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-18 17:16:26 -05:00
Satya Priya Kakitapalli
691f3413ba clk: qcom: camcc-sc8180x: Add SC8180X camera clock controller driver 
Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on SC8180X platform.

Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-3-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:15:49 -05:00
Bjorn Andersson
910ad0190c Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17 
Merge topic branch with missing GCC clocks and the camera clock
controller for SC8180X through a topic branch, to make it available for
DeviceTree inclusion as well.
 2025-06-10 22:14:41 -05:00
Satya Priya Kakitapalli
b5975ce461 dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller 
Add device tree bindings for the camera clock controller on
Qualcomm SC8180X platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:14:31 -05:00
Satya Priya Kakitapalli
19ac3579af dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x 
The multi-media AHB clocks are needed to create HW dependency in
the multimedia CC dt blocks and avoid any issues. They were not
defined in the initial bindings. Add all the missing clock bindings
for gcc-sc8180x.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-1-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:14:31 -05:00
Krzysztof Kozlowski
0acf9e65a4 clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks 
On SM8750 the setting rate of pixel and byte clocks, while the parent
DSI PHY PLL, fails with:

  disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.

DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in
CMN_CTRL_0 asserted.

Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is
enabled during rate changes.

Cc: stable@vger.kernel.org
Fixes: f1080d8dab ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250520090741.45820-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:13:06 -05:00
Christian Marangi
077ec7bcec clk: qcom: gcc-ipq8074: fix broken freq table for nss_port6_tx_clk_src 
With the conversion done by commit e88f03230d ("clk: qcom: gcc-ipq8074:
rework nss_port5/6 clock to multiple conf") a Copy-Paste error was made
for the nss_port6_tx_clk_src frequency table.

This was caused by the wrong setting of the parent in
ftbl_nss_port6_tx_clk_src that was wrongly set to P_UNIPHY1_RX instead
of P_UNIPHY2_TX.

This cause the UNIPHY2 port to malfunction when it needs to be scaled to
higher clock. The malfunction was observed with the example scenario
with an Aquantia 10G PHY connected and a speed higher than 1G (example
2.5G)

Fix the broken frequency table to restore original functionality.

Cc: stable@vger.kernel.org
Fixes: e88f03230d ("clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20250522202600.4028-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:12:47 -05:00
Taniya Das
9ed3eccdfd clk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's 
The video driver will be using the newly introduced
dev_pm_genpd_set_hwmode() API to switch the video GDSC to HW and SW
control modes at runtime.
Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's for
Qualcomm SoC SC7180, SDM845, SM7150, SM8150 and SM8450.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com>
Link: https://lore.kernel.org/r/20250530-switch_gdsc_mode-v5-1-657c56313351@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 22:12:39 -05:00
Konrad Dybcio
720b1e8f20 clk: qcom: Add video clock controller driver for SM6350 
Add support for the video clock controller found on SM6350 based
devices.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konradybcio@kernel.org>
Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-3-cc22386433f4@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 14:58:13 -05:00
Jagadeesh Kona
d7eddaf0ed clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe 
Camera PLLs on X1E80100 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management,
PLL configuration and enabling critical clocks to qcom_cc_really_probe()
which ensures all required power domains are in enabled state before
configuring the PLLs or enabling the clocks.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # Dell Inspiron
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-12-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:20 -05:00
Jagadeesh Kona
3f8dd231e6 clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe 
Camera PLLs on SM8650 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management,
PLL configuration and enabling critical clocks to qcom_cc_really_probe()
which ensures all required power domains are in enabled state before
configuring the PLLs or enabling the clocks.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-11-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:20 -05:00
Jagadeesh Kona
adb50c762f clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe 
Camera PLLs on SM8550 require both MMCX and MXC rails to be kept ON to
configure the PLLs properly. Hence move runtime power management, PLL
configuration and enabling critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-10-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:20 -05:00
Jagadeesh Kona
eb65d754eb clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe 
Camera PLLs on SM8450/SM8475 require both MMCX and MXC rails to be
kept ON to configure the PLLs properly. Hence move runtime power
management, PLL configuration and enable critical clocks to
qcom_cc_really_probe() which ensures all required power domains are in
enabled state before configuring the PLLs or enabling the clocks.

This change also removes the modelling for cam_cc_gdsc_clk and keeps it
always ON from probe since using CLK_IS_CRITICAL will prevent the clock
controller associated power domains from collapsing due to clock framework
invoking clk_pm_runtime_get() during prepare.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-9-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:20 -05:00
Jagadeesh Kona
a9dc2cc727 clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe 
Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-8-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:20 -05:00
Jagadeesh Kona
512af5bf31 clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe 
Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00
Jagadeesh Kona
452ae64997 clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe 
Add support to configure PLLS and clk registers in qcom_cc_really_probe().
This ensures all required power domains are enabled and kept ON by runtime
PM code in qcom_cc_really_probe() before configuring the PLLS or clock
registers.

Add support for qcom_cc_driver_data struct to maintain the clock
controllers PLLs and CBCRs data, and a pointer of it can be stored in
clock descriptor structure. If any clock controller driver requires to
program some additional misc register settings, it can register the
clk_regs_configure() callback in the driver data.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-6-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00
Jagadeesh Kona
c0b6627369 clk: qcom: common: Handle runtime power management in qcom_cc_really_probe 
Add support for runtime power management in qcom_cc_really_probe() to
commonize it across all the clock controllers. The runtime power management
is not required for all clock controllers, hence handle the rpm based on
use_rpm flag in clock controller descriptor.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-5-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00
Taniya Das
0f698c1635 clk: qcom: clk-alpha-pll: Add support for common PLL configuration function 
To properly configure the PLLs on recent chipsets, it often requires more
than one power domain to be kept ON. The support to enable multiple power
domains is being added in qcom_cc_really_probe() and PLLs should be
configured post all the required power domains are enabled.

Hence integrate PLL configuration into clk_alpha_pll structure and add
support for qcom_clk_alpha_pll_configure() function which can be called
from qcom_cc_really_probe() to configure the clock controller PLLs after
all required power domains are enabled.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-4-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-06-10 12:59:19 -05:00