pinconf_generic_parse_dt_config() takes a node as input and generates an
array of generic pinconfig values from the properties of this node.
As I couldn't find a mechanism to count the number of properties of a node
the function uses internally an array to accept one of parameter and copies
the real present options to a smaller variable at its end.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html
With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.
Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.
[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
(9e605cb68a),
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dove power management unit can mux some special functions to mpp0-15.
This patch adds support to set/get the current PMU function mapped
to the corresponding mpp pins. The device tree documentation is also
updated accordingly.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.
The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller instead. We solve this by forwarding the external
interrupt from the main controller into the irq domain of the pin bank.
The masking/acking of these interrupts is handled in the same way.
Furthermore the S3C2412/2413 SoCs contain another oddity in that they
keep the same 4 eints in the main interrupt controller and eintpend
register and requiring ack operations to happen in both. This is solved
by using different compatible properties for the wakeup eint node which
set a property accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Pull ARM SoC device tree updates (part 2) from Arnd Bergmann:
"These are mostly new device tree bindings for existing drivers, as
well as changes to the device tree source files to add support for
those devices, and a couple of new boards, most notably Samsung's
Exynos5 based Chromebook.
The changes depend on earlier platform specific updates and touch the
usual platforms: omap, exynos, tegra, mxs, mvebu and davinci."
* tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: exynos: dts: cros5250: add EC device
ARM: dts: Add sbs-battery for exynos5250-snow
ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
ARM: dts: add mshc controller node for Exynos4x12 SoCs
ARM: dts: Add chip-id controller node on Exynos4/5 SoC
ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
ARM: davinci: da850-evm: add SPI flash support
ARM: davinci: da850: override SPI DT node device name
ARM: davinci: da850: add SPI1 DT node
spi/davinci: add DT binding documentation
spi/davinci: no wildcards in DT compatible property
ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
ARM: dts: mvebu: introduce internal-regs node
ARM: dts: mvebu: Convert all the mvebu files to use the range property
ARM: dts: mvebu: move all peripherals inside soc
ARM: dts: mvebu: fix cpus section indentation
ARM: davinci: da850: add EHRPWM & ECAP DT node
ARM/dts: OMAP3: fix pinctrl-single configuration
ARM: dts: Add OMAP3430 SDP NOR flash memory binding
ARM: dts: Add NOR flash bindings for OMAP2420 H4
...
Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.
Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
...
Pull ARM SoC device-tree updates from Olof Johansson:
"Part 1 of device-tree updates for 3.10. The bulk of the churn in this
branch is due to i.MX moving from C-defined pin control over to device
tree, which is a one-time conversion that will allow greater
flexibility down the road.
Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
handful of cleanups to tegra due to the new include file functionality
of the device tree compiler"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits)
arm: mvebu: PCIe Device Tree informations for Armada XP GP
arm: mvebu: PCIe Device Tree informations for Armada 370 DB
arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
arm: mvebu: PCIe Device Tree informations for Armada XP DB
arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
arm: mvebu: add PCIe Device Tree informations for Armada XP
arm: mvebu: add PCIe Device Tree informations for Armada 370
ARM: sunxi: unify osc24M_fixed and osc24M
arm: vt8500: Add SDHC support to WM8505 DT
ARM: dts: Add a 64 bits version of the skeleton device tree
ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
ARM: dts: imx6dl-wandboard: Add USB Host support
ARM: dts: imx51 cpu node
ARM: dts: Add missing imx27-phytec-phycore dtb target
ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module
ARM: i.MX51: Add PATA support
ARM: dts: Add initial support for Wandboard Dual-Lite
...
The imx6dl is a derivative of imx6q with very limited difference. These
two SoCs are so compatible that they can be handled as one platform in
software. That said, we will not have target SOC_IMX6DL but just
reusing SOC_IMX6Q. That's why the pinctrl-imx6dl driver is added here
with symbol PINCTRL_IMX6Q controlling the build of it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some pins on the i.mx23 and i.mx28 are missing pull-ups, document that
oddity because it was difficult to know the expected behaviour.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.
Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.
All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Pull non-critical ARM SoC bug fixes from Arnd Bergmann:
"Bug fixes that did not make it into v3.8, mostly because they were not
considered important enough, and in some cases because bugs only show
up in combination with other patches destined for 3.9. This includes
a few larger patches for GPIO on the Marvell PXA platform and a lot of
Samsung specific bug fixes, as well as a series from Arnd to fix older
build warnings."
* tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
ARM: SPEAr13xx: Enable CONFIG_ARCH_HAS_CPUFREQ
ARM: imx: MACH_MX31ADS_WM1133_EV1 needs REGULATOR_WM8350
scripts/sortextable: silence script output
ARM: s3c: i2c: add platform_device forward declaration
ARM: mvebu: allow selecting mvebu without Armada XP
ARM: pick Versatile by default for !MMU
ARM: integrator: fix build with INTEGRATOR_AP off
ARM: integrator/versatile: fix NOMMU warnings
ARM: sa1100: don't warn about mach/ide.h
ARM: shmobile: fix defconfig warning on CONFIG_USB
ARM: w90x900: fix legacy assembly syntax
ARM: samsung: fix assembly syntax for new gas
ARM: disable virt_to_bus/virt_to_bus almost everywhere
ARM: dts: Correct pin configuration of SD 4 for exynos4x12-pinctrl
ARM: SAMSUNG: Silence empty switch warning in fimc-core.h
ARM: SAMSUNG: Silence empty switch warning in sdhci.h
ARM: msm: proc_comm_boot_wait should not be __init
arm: vt8500: Update MAINTAINERS entry for arch-vt8500
ARM: integrator: ensure ap_syscon_base is initialised when !CONFIG_MMU
ARM: S5PV210: Fix early uart output in fifo mode
...
Pull pinctrl changes from Linus Walleij:
"These are the main pinctrl changes for the v3.9 merge window. The
most interesting change by far is how the device core grabs pinctrl
default handles avoiding the need to stick boilerplate into driver
consumers.
- Grabbing of default pinctrl handles from the device core. These
are the hunks hitting drivers/base. All is ACKed by Greg, after a
long discussion about different alternatives.
- Some stuff also touches the MFD and ARM SoC trees, this has been
coordinated and ACKed.
- New drivers for:
- The Tegra 114 sub-SoC
- Allwinner sunxi
- New ABx500 driver and sub-SoC drivers for AB8500, AB8505, AB9540
and AB8540.
- Make it possible for hogged pins to enter a sleep mode, and make it
possible for drivers to control that mode.
- Various clean-up, extensions and device tree support to various pin
controllers."
* tag 'pinctrl-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (68 commits)
pinctrl: tegra: add clfvs function to Tegra114 support
pinctrl: generic: rename input schmitt disable
pinctrl/pinconfig: add debug interface
pinctrl: samsung: remove duplicated line
ARM: ux500: use real AB8500 IRQ numbers instead of virtual ones
ARM: ux500: remove irq_base property from platform_data
pinctrl/abx500: use direct IRQ defines
pinctrl/abx500: replace IRQ offsets with table read-in values
pinctrl/abx500: move IRQ handling to ab8500-core
pinctrl: exynos5440: remove erroneous __init
pinctrl/abx500: adjust offset for get_mode()
pinctrl/abx500: add Device Tree support
pinctrl/abx500: align GPIO cluster boundaries
pinctrl/abx500: prevent error path from corrupting returning error
pinctrl: sunxi: add of_xlate function
pinctrl/lantiq: fix pin number in ltq_pmx_gpio_request_enable
pinctrl/lantiq: add functionality to falcon_pinconf_dbg_show
pinctrl/lantiq: fix pinconfig parameters
pinctrl/lantiq: one of the boot leds was defined incorrectly
pinctrl/lantiq: only probe available pad controllers
...
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.
This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.
This driver only implements the pinctrl part, the gpio part will come
eventually.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.
The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.
This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".
Originally written by Pritesh.
ldewangan:
- cleanup the patches,
- remove non-require tables.
- Use module_platform_driver() for driver registartion.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
commit 7bec207427 remove sirfsoc_gpio_set_pull function,
this patches takes the feature back by adding sirf,pullups and
sirf,pulldowns prop in dts, and the driver will set the GPIO
pull according to the dts.
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
While sending email to Linus for reviewing:
"pinctrl: sirf: add DT-binding pinmux mapping support"
https://patchwork.kernel.org/patch/1364361/
i have included the devicetree/bindings/pinctrl/pinctrl-sirf.txt
But while sending pull request with commit 056876f6c7,
i missed the document.
this patch takes the document back.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pull ARM SoC device tree conversions and enablement from Olof Johansson:
"Continued device tree conversion and enablement across a number of
platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
smaller series as well.
ux500 has seen continued conversion for platforms. Several platforms
have seen pinctrl-via-devicetree conversions for simpler
multiplatform. Tegra is adding data for new devices/drivers, and
Exynos has a bunch of new bindings and devices added as well.
So, pretty much the same progression in the right direction as the
last few releases."
Fix up conflicts as per Olof.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits)
ARM: ux500: Rename dbx500 cpufreq code to be more generic
ARM: dts: add missing ux500 device trees
ARM: ux500: Stop registering the PCM driver from platform code
ARM: ux500: Move board specific GPIO info out to subordinate DTS files
ARM: ux500: Disable the MMCI gpio-regulator by default
ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
ARM: Kirkwood: Add support LED of OpenBlocks A6
ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
ARM: kirkwood: Add support DT of second I2C bus
ARM: kirkwood: Convert mplcec4 board to pinctrl
ARM: Kirkwood: Convert km_kirkwood to pinctrl
ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
ARM: Kirkwood: Convert IX2-200 to pinctrl.
ARM: Kirkwood: Convert lsxl boards to pinctrl.
ARM: Kirkwood: Convert ib62x0 to pinctrl.
ARM: Kirkwood: Convert GoFlex Net to pinctrl.
ARM: Kirkwood: Convert dreamplug to pinctrl.
ARM: Kirkwood: Convert dockstar to pinctrl.
...
Pull ARM SoC updates from Olof Johansson:
"This contains the bulk of new SoC development for this merge window.
Two new platforms have been added, the sunxi platforms (Allwinner A1x
SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
series of ARMv7 platforms from them, where the hope is that we can
keep the platform code generic enough to have them all share one mach
directory. The new Broadcom platform is contributed by Christian
Daudt.
Highbank has grown support for Calxeda's next generation of hardware,
ECX-2000.
clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
also taken on maintainership of the platform.
Beyond this there has been a bunch of work from a number of people on
converting more platforms to IRQ domains, pinctrl conversion, cleanup
and general feature enablement across most of the active platforms."
Fix up trivial conflicts as per Olof.
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
mfd: vexpress-sysreg: Remove LEDs code
irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
irq: versatile: delete dangling variable
ARM: sunxi: add missing include for mdelay()
ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
ARM: dts: add node for PL330 MDMA1 controller for exynos4
ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
ARM: EXYNOS: add UART3 to DEBUG_LL ports
ARM: S3C24XX: Add clkdev entry for camif-upll clock
ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
ARM: sunxi: Add missing sun4i.dtsi file
pinctrl: samsung: Do not initialise statics to 0
ARM i.MX6: remove gate_mask from pllv3
ARM i.MX6: Fix ethernet PLL clocks
ARM i.MX6: rename PLLs according to datasheet
ARM i.MX6: Add pwm support
ARM i.MX51: Add pwm support
ARM i.MX53: Add pwm support
ARM: mx5: Replace clk_register_clkdev with clock DT lookup
...
From Jason Cooper:
orion dt for v3.8
- ehci-orion dt binding
- gpio-poweroff
- use dt regulators
- move mpp to DT/pinctrl
Depends on:
- orion/boards
- merge conflicts
- keep all 'select's in Kconfig
- remove all #includes in board-*.c
- pinctrl/devel up to:
- 06763c7 pinctrl: mvebu: move to its own directory
* tag 'orion_dt_for_3.8' of git://git.infradead.org/users/jcooper/linux: (211 commits)
ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
ARM: Kirkwood: Add support LED of OpenBlocks A6
ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
ARM: kirkwood: Add support DT of second I2C bus
ARM: kirkwood: Convert mplcec4 board to pinctrl
ARM: Kirkwood: Convert km_kirkwood to pinctrl
ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
ARM: Kirkwood: Convert IX2-200 to pinctrl.
ARM: Kirkwood: Convert lsxl boards to pinctrl.
ARM: Kirkwood: Convert ib62x0 to pinctrl.
ARM: Kirkwood: Convert GoFlex Net to pinctrl.
ARM: Kirkwood: Convert dreamplug to pinctrl.
ARM: Kirkwood: Convert dockstar to pinctrl.
ARM: Kirkwood: Convert dnskw to pinctrl
ARM: Kirkwood: Convert iConnect to pinctrl.
ARM: Kirkwood: Convert TS219 to pinctrl.
ARM: Kirkwood: Add DTSI files for pinctrl
ARM: Kirkwood: Make use of mvebu pincltl and gpio drivers
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The Marvell 98DX412x SoC embed a kirkwood variant that does not have
pinctrl support yet. Even though this kirkwood is very similar to the
88f6281, on the MPP front a lot of pins are not available. That's why a
new kirkwood pinctrl variant is needed.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This is also include the gpio controller as the IP share both.
Each soc will have to describe the SoC limitation and pin configuration via
DT.
This will allow to do not need to touch the C code when adding new SoC if the
IP version is supported.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Pull MIPS update from Ralf Baechle:
"This is the MIPS update for 3.7.
A fair chunk of them are platform updates to the Cavium Octeon SOC
(which involves machine generated header files of considerable size),
Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
platforms.
Support for the commercial MIPS simulator MIPSsim has been removed as
MIPS Technologies is shifting away from this product and Qemu is
offering various more powerful platforms. The generic MIPS code can
now also probe for no-execute / write-only TLB features implemented
without the full SmartMIPS extension as permitted by the latest MIPS
processor architecture. Lots of small changes to generic code."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
MIPS: BCM63XX: Properly handle mac address octet overflow
MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
MIPS: Replace `-' in defconfig filename wth `_' for consistency.
MIPS: Wire kcmp syscall.
MIPS: MIPSsim: Remove the MIPSsim platform.
MIPS: NOTIFY_RESUME is not needed in TIF masks
MIPS: Merge the identical "return from syscall" per-ABI code
MIPS: Unobfuscate _TIF..._MASK
MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
MIPS: Add base architecture support for RI and XI.
MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
MIPS: uasm: Add INS and EXT instructions.
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
MIPS: Make VPE count to be one-based.
MIPS: Add new end of interrupt functionality for GIC.
MIPS: Add EIC support for GIC.
MIPS: Code clean-ups for the GIC.
...
Pull late ARM soc platform updates from Olof Johansson:
"This branch contains updates to OMAP and Marvell platforms (kirkwood,
dove, mvebu) that came in after we had done the big multiplatform
merges, so they were kept separate from the rest, and not separated
into the traditional topics of cleanup/driver/platform features.
For OMAP, the updates are:
- Runtime PM conversions for the GPMC and RNG IP blocks
- Preparation patches for the OMAP common clock framework conversion
- clkdev alias additions required by other drivers
- Performance Monitoring Unit (PMU) support for OMAP2, 3, and
non-4430 OMAP4
- OMAP hwmod code and data improvements
- Preparation patches for the IOMMU runtime PM conversion
- Preparation patches for OMAP4 full-chip retention support
For Kirkwood/Dove/mvebu:
- New driver for "address decoder controller" for mvebu, which is a
piece of hardware that configures addressable devices and
peripherals. First user is the boot rom aperture on armada XP
since it is needed for SMP support.
- New device tree bindings for peripherals such as gpio-fan, iconnect
nand, mv_cesa and the above address decoder controller.
- Some defconfig updates, mostly to enable new DT boards and a few
drivers.
- New drivers using the pincontrol subsystem for dove, kirkwood and
mvebu
- New clean gpio driver for mvebu"
* tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits)
ARM: mvebu: fix build breaks from multi-platform conversion
ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70
ARM: OMAP2+: PMU: Add runtime PM support
ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD
ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD
ARM: OMAP3: hwmod data: Add debugss HWMOD data
ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
hwrng: OMAP: remove SoC restrictions from driver registration
ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
hwrng: OMAP: convert to use runtime PM
hwrng: OMAP: store per-device data in per-device variables, not file statics
ARM: OMAP2xxx: hwmod/CM: add RNG integration data
ARM: OMAP2+: gpmc: minimal driver support
ARM: OMAP2+: gpmc: Adapt to HWMOD
ARM: OMAP2/3: hwmod data: add gpmc
ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp
ARM: OMAP3: hwmod data: add mmu data for iva and isp
ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected
ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks
...
Pull pinctrl changes from Linus Walleij:
"Some of this stuff is hitting arch/arm/* and have been ACKed by the
ARM SoC folks, or it's device tree bindings pertaining to the specific
driver.
These are the bulk pinctrl changes for kernel v3.7:
- Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
provide platform config for the Nomadik.
- Add a driver for the i.MX35.
- Add a driver for the BCM2835, an advanced GPIO expander.
- Various fixes and clean-ups and minor improvements for the core,
Nomadik, pinctr-single, sirf drivers.
- Some platform config for the ux500."
* tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits)
pinctrl: add bcm2835 driver
pinctrl: clarify idle vs sleep states
pinctrl/nomadik: use irq_find_mapping()
pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq
pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range
pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input
pinctrl: sirf: add missing pins to pinctrl list
pinctrl: sirf: fix a typo in sirfsoc_gpio_probe
pinctrl: pinctrl-single: add debugfs pin h/w state info
ARM: ux500: 8500: update I2C sleep states pinctrl
pinctrl: Fix potential memory leak in pinctrl_register_one_pin()
ARM: ux500: tidy up pin sleep modes
ARM: ux500: fix spi2 pin group
pinctrl: imx: remove duplicated const
pinctrl: document semantics vs GPIO
ARM: ux500: 8500: use hsit_a_2 group for HSI
pinctrl: use kasprintf() in pinmux_request_gpio()
pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux
pinctrl/nomadik : add MC1_a_2 pin MC1 function group list
pinctrl: pinctrl-single: Make sure we do not change bits outside of mask
...
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.
Original driver by Simon Arlott.
Rewrite including GPIO chip device by Chris Boot.
Upstreaming changes by Stephen Warren:
* Wrote DT binding documentation.
* Changed brcm,function to an integer to more directly match the
datasheet, and to match brcm,pins being an integer.
* Implemented pull-up/down pin config.
* Removed read-only DT property and related code. The restriction this
implemented are driven by the board, not the GPIO HW block, so don't
really make sense of a HW block binding, were in general incomplete
(since they could only know about the few pins hard-coded into the
Raspberry Pi B board design and not the uncommitted GPIOS), and are
better represented simply by not writing incorrect data into pin
configuration nodes.
* Don't set GPIO_IN function select in gpio_request_enable() to avoid
glitches; defer this to gpio_set_direction(). Consequently, removed
empty bcm2835_pmx_gpio_request_enable().
* Simplified enabled_irq_map[]; make it explicitly 1 entry per bank.
* Lifted use of enabled_irq_map[] outside the per-interrupt loop in
IRQ handler, thus fixing an issue where the code was indexing into
enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID.
* Removed locking in IRQ handler, since all other code uses
spin_lock_irqsave() and so guarantees it doesn't run concurrently
with the handler.
* Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of
bcm2835_gpio_pins[].
* Remove range-checking from bcm2835_pctl_get_groups_count() since we've
decided to trust the pinctrl core.
* Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set()
directly for simplicity.
* Fixed body of dt_free_map() to match latest dt_node_to_map().
* Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl
core owns doing this.
* Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more
descriptive.
* Simplified remove(); removed call to non-existent
pinctrl_remove_gpio_range(), remove early return on error.
* Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's
base GPIO number.
* Error-handling cleanups in probe().
* Switched to module_platform_driver() rather than open-coding.
* Made pin, group, and function names lower-case.
* s/broadcom/brcm/ in DT property names.
* s/2708/2835/.
* Fixed a couple minor checkpatch warnings, and other minor cleanup.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
