With the SION bit set a pin can be read as GPIO even though it's not muxed
as GPIO. This is useful at times. The downside however is that the signal
is not only routed to the GPIO IP but also all other IPs that can make use
of the pin. This resulted in more than one issue for me in the past. Things
like spi transfers that result in usb reenumeration or setting a GPIO to a
value that triggers an RTS irq for an UART.
This convinces me that the SION bit does more harm than good and so all
SION bits are removed that are not known to be needed.
Note that this has no influence on GPIOs under Linux as the gpio-mxc
driver just reports the level the pin is driven to for outputs and not
the level as seen on the pin.
If this commit introduces a regression for you, please report which SION
bit is essential for your setup.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On these two boards, the serial0 is used for inter-chip connection,
so cannot be used for login console. The serial2 is used instead
for them, but it is tedious to use because upper level deployment
projects must switch login console per board.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This pin-muxing is needed to get access to the UniPhier System Bus.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Name the Pin Function Controller subnode for SCIFA4 after its device
name, instead of after the serial port alias.
This avoids conflicts when adding support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF2 after its device
name, instead of using some arbitrary name that looks like a serial port
alias, but differs from the actual alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF2 after its device
name, instead of using some arbitrary name that looks like a serial port
alias, but differs from the actual alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF0 and SCIF1 after
their device names, instead of after the serial port aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF0 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for QSPI and MSIOF0 after
their device names, instead of after the spi interface aliases.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF0 and SCIF1 after
their device names, instead of after the serial port aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for VIN1 after its device name,
instead of using the generic and indexless "vin".
This avoids conflicts when enabling support for more video inputs later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for QSPI and MSIOF1 after
their device names, instead of after the spi interface aliases.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF0 and SCIFA1 after
their device names, instead of after the serial port aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF2 and SCIF4 after
their device names, instead of using some arbitrary names that look like
serial port aliases, but differ from the actual aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF0 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIFA1 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for MMC0 after its device name,
instead of using the generic and indexless "mmc".
This avoids conflicts when enabling support for more MMC interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIFA0 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fixes for Exynos-based Snow and Peach Pit boards for regressions introduced in
4.7-rc1 because OF graph logic expects specific names of child nodes.
* tag 'samsung-fixes-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Fix port nodes names for Exynos5420 Peach Pit board
ARM: dts: exynos: Fix port nodes names for Exynos5250 Snow board
Signed-off-by: Olof Johansson <olof@lixom.net>
SoCFPGA DTS updates for v4.8
- Update Arria10 ECC manager
- Add ethernet alias for Arria10
- Update serial alias for Arria10
* tag 'socfpga_updates_v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: fix definitions of serial console
ARM: dts: socfpga: add ethernet alias on Arria10
ARM: dts: Move Arria10 SDRAM as child of ECC Manager
ARM: dts: Arria10 ECC Manager IRQ controller changes
Signed-off-by: Olof Johansson <olof@lixom.net>
Ux500 devicetree patches:
- Move the ab8500 compatible string from the board to the
chipset.
- Define GPIO line names for the boards.
* tag 'ux500-dt-asoc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: UX500: name the GPIO lines on HREFv60plus
ARM: dts: Ux500: name the GPIO lines on Snowball
ARM: dts: Ux500: move compatible string to chipset
Signed-off-by: Olof Johansson <olof@lixom.net>
Topic branch for adding Exynos 5410 Odroid XU board for v4.8.
This brings support for Hardkernel's Odroid XU board. It was the first
design with big.LITTLE SoC from Samsung: Exynos5410. The board is not
very popular. Newer XU3 and XU4 got more attention.
Board details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
revisions though),
6. eMMC 4.5 and microSD slots.
* tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410
ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board
ARM: dts: exynos: Add Thermal Management Unit to Exynos5410
ARM: dts: exynos: Interrupt for USB DWC3-1 differs between Exynos5420 and 5410
dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410
dt-bindings: clock: Add TMU clock ID to Exynos5410
ARM: dts: exynos: Add RTC and I2C to Exynos5410
ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410
ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi
ARM: dts: exynos: Add initial support for Odroid XU board
ARM: dts: exynos: Add USB to Exynos5410
ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap
ARM: dts: exynos: Enable UART3 on Exynos5410
ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi
ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi
ARM: dts: exynos: Move common nodes to exynos5.dtsi
ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Define the port mapping for the SmartRG SR400ACE device.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add interrupt mapping for the Switch Register Access Block. Only 12
interrupts are usable at the moment even though up to 32 are dedicated
to the SRAB.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the Switch Register Access Block which is a special piece of
hardware allowing us to perform indirect read/writes towards the
integrated BCM5301X Ethernet switch.
We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi
bus node to get proper binding between the BCMA instantiated core and
the Device Tree nodes. We will need that to be able to reference
Ethernet Device Tree nodes in a future patch adding the switch ports
layout.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The #size-cells for the pmics are 0, but we specify a size in the
reg property so that MPP and GPIO modules can figure out how many
pins there are. Now that we've done that by counting irqs, we can
remove the size elements in the reg properties and be DT
compliant.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Enable the sdcard slot and wire up the regulators for the two
storage controllers found on the apq8074 dragonboard.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the appropriate min/max voltages for the regulators on the
apq8074 dragonboard so that they can be used by clients properly.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PCI reset GPIO is active low, so represent it with the
GPIO_ACTIVE_LOW flag.
Even though the imx6 PCI driver will not take the polarity into account
in this case, it is better to provide a correct description in device-tree.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
GPLv2-only devicetrees make reuse difficult for software components
licensed under a different license. In particular, the Utilite Pro
devicetree file (which includes imx6q-cm-fx6.dts) is already dual
licensed under GPLv2/X11.
Hence, relicense imx6q-cm-fx6.dts under GPLv2/X11 dual license.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The CompuLab Utilite Pro is a miniature fanless desktop pc based on
the i.MX6 Quad powered cm-fx6 module. It features two serial ports,
USB OTG, 4x USB, analog audio and S/PDIF, 2x Gb Ethernet, HDMI and
DVI ports, an on-board 32GB SSD, a mmc slot, and on-board wifi/bt.
Add initial support for it including USB, Ethernet (both ports), sata
and HDMI support.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The cm-fx6 module has an on-board spi-flash chip for its firmware, an
eeprom (containing e.g. the mac address of the on-board Ethernet),
a sata port, a pcie controller, an USB hub, and an USB otg port.
Enable support for them. In addition, enable syscon poweroff support.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
