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Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost
identical to the one available in RZ/G2{L,UL}, the exception being some
core clocks as follows:
- The SD clock is composed of a mux and a divider, and the divider
has some limitations (div = 1 cannot be set if mux rate is 800MHz),
- There are 3 SD clocks,
- The OCTA and TSU clocks are specific to RZ/G3S,
- PLL1/4/6 are specific to RZ/G3S with its own computation formula.
Even with this RZ/G3S could use the same bindings as RZ/G2L.
Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse
Generator (CPG) core clocks, module clocks and resets were added.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-13-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
90 lines
2.7 KiB
YAML
90 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
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Standby Mode share the same register block. On RZ/V2M, the functionality is
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similar, but does not have Clock Monitor Registers.
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They provide the following functionalities:
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- The CPG block generates various core clocks,
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- The Module Standby Mode block provides two functions:
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1. Module Standby, providing a Clock Domain to control the clock supply
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to individual SoC devices,
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2. Reset Control, to perform a software reset of individual SoC devices.
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properties:
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compatible:
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enum:
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- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
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- renesas,r9a07g044-cpg # RZ/G2{L,LC}
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- renesas,r9a07g054-cpg # RZ/V2L
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- renesas,r9a08g045-cpg # RZ/G3S
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- renesas,r9a09g011-cpg # RZ/V2M
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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description:
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Clock source to CPG can be either from external clock input (EXCLK) or
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crystal oscillator (XIN/XOUT).
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const: extal
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/r9a0*-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
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const: 2
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'#power-domain-cells':
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description:
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SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
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can be power-managed through Module Standby should refer to the CPG device
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node in their "power-domains" property, as documented by the generic PM
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Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the module number, as defined in
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<dt-bindings/clock/r9a0*-cpg.h>.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a07g044-cpg";
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reg = <0x11010000 0x10000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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