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32b6ff95b9
CDM block supports formats other than H1V2 for DP. Since we are now
adding support for CDM over DP, relax the checks to allow all other
formats for DP other than H1V2.
Changes in v2:
- Add fixes tag
- Move patch to top of series
Fixes: 0afac0ba60 ("drm/msm/dpu: add dpu_hw_cdm abstraction for CDM block")
Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579606/
Link: https://lore.kernel.org/r/20240222194025.25329-2-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
248 lines
6.8 KiB
C
248 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <drm/drm_managed.h>
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_cdm.h"
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#include "dpu_kms.h"
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#define CDM_CSC_10_OPMODE 0x000
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#define CDM_CSC_10_BASE 0x004
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#define CDM_CDWN2_OP_MODE 0x100
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#define CDM_CDWN2_CLAMP_OUT 0x104
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#define CDM_CDWN2_PARAMS_3D_0 0x108
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#define CDM_CDWN2_PARAMS_3D_1 0x10C
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#define CDM_CDWN2_COEFF_COSITE_H_0 0x110
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#define CDM_CDWN2_COEFF_COSITE_H_1 0x114
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#define CDM_CDWN2_COEFF_COSITE_H_2 0x118
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#define CDM_CDWN2_COEFF_OFFSITE_H_0 0x11C
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#define CDM_CDWN2_COEFF_OFFSITE_H_1 0x120
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#define CDM_CDWN2_COEFF_OFFSITE_H_2 0x124
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#define CDM_CDWN2_COEFF_COSITE_V 0x128
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#define CDM_CDWN2_COEFF_OFFSITE_V 0x12C
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#define CDM_CDWN2_OUT_SIZE 0x130
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#define CDM_HDMI_PACK_OP_MODE 0x200
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#define CDM_CSC_10_MATRIX_COEFF_0 0x004
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#define CDM_MUX 0x224
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/* CDM CDWN2 sub-block bit definitions */
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#define CDM_CDWN2_OP_MODE_EN BIT(0)
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#define CDM_CDWN2_OP_MODE_ENABLE_H BIT(1)
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#define CDM_CDWN2_OP_MODE_ENABLE_V BIT(2)
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#define CDM_CDWN2_OP_MODE_BITS_OUT_8BIT BIT(7)
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#define CDM_CDWN2_V_PIXEL_METHOD_MASK GENMASK(6, 5)
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#define CDM_CDWN2_H_PIXEL_METHOD_MASK GENMASK(4, 3)
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/* CDM CSC10 sub-block bit definitions */
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#define CDM_CSC10_OP_MODE_EN BIT(0)
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#define CDM_CSC10_OP_MODE_SRC_FMT_YUV BIT(1)
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#define CDM_CSC10_OP_MODE_DST_FMT_YUV BIT(2)
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/* CDM HDMI pack sub-block bit definitions */
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#define CDM_HDMI_PACK_OP_MODE_EN BIT(0)
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/*
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* Horizontal coefficients for cosite chroma downscale
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* s13 representation of coefficients
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*/
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static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
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/*
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* Horizontal coefficients for offsite chroma downscale
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*/
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static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
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/*
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* Vertical coefficients for cosite chroma downscale
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*/
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static u32 cosite_v_coeff[] = {0x00080004};
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/*
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* Vertical coefficients for offsite chroma downscale
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*/
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static u32 offsite_v_coeff[] = {0x00060002};
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static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 opmode;
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u32 out_size;
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switch (cfg->h_cdwn_type) {
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case CDM_CDWN_DISABLE:
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opmode = 0;
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break;
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case CDM_CDWN_PIXEL_DROP:
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opmode = CDM_CDWN2_OP_MODE_ENABLE_H |
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FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_PIXEL_DROP);
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break;
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case CDM_CDWN_AVG:
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opmode = CDM_CDWN2_OP_MODE_ENABLE_H |
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FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_AVG);
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break;
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case CDM_CDWN_COSITE:
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opmode = CDM_CDWN2_OP_MODE_ENABLE_H |
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FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_COSITE);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,
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cosite_h_coeff[0]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,
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cosite_h_coeff[1]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,
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cosite_h_coeff[2]);
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break;
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case CDM_CDWN_OFFSITE:
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opmode = CDM_CDWN2_OP_MODE_ENABLE_H |
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FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK, CDM_CDWN2_METHOD_OFFSITE);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,
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offsite_h_coeff[0]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,
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offsite_h_coeff[1]);
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DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,
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offsite_h_coeff[2]);
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break;
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default:
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DPU_ERROR("%s invalid horz down sampling type\n", __func__);
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return -EINVAL;
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}
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switch (cfg->v_cdwn_type) {
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case CDM_CDWN_DISABLE:
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/* if its only Horizontal downsample, we dont need to do anything here */
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break;
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case CDM_CDWN_PIXEL_DROP:
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opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |
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FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_PIXEL_DROP);
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break;
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case CDM_CDWN_AVG:
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opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |
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FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_AVG);
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break;
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case CDM_CDWN_COSITE:
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opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |
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FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_COSITE);
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DPU_REG_WRITE(c,
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CDM_CDWN2_COEFF_COSITE_V,
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cosite_v_coeff[0]);
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break;
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case CDM_CDWN_OFFSITE:
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opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |
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FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,
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CDM_CDWN2_METHOD_OFFSITE);
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DPU_REG_WRITE(c,
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CDM_CDWN2_COEFF_OFFSITE_V,
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offsite_v_coeff[0]);
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break;
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default:
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return -EINVAL;
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}
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if (cfg->output_bit_depth != CDM_CDWN_OUTPUT_10BIT)
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opmode |= CDM_CDWN2_OP_MODE_BITS_OUT_8BIT;
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if (cfg->v_cdwn_type || cfg->h_cdwn_type)
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opmode |= CDM_CDWN2_OP_MODE_EN; /* EN CDWN module */
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else
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opmode &= ~CDM_CDWN2_OP_MODE_EN;
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out_size = (cfg->output_width & 0xFFFF) | ((cfg->output_height & 0xFFFF) << 16);
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DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);
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DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);
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DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT, ((0x3FF << 16) | 0x0));
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return 0;
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}
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static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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const struct dpu_format *fmt;
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u32 opmode = 0;
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u32 csc = 0;
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if (!ctx || !cdm)
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return -EINVAL;
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fmt = cdm->output_fmt;
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if (!DPU_FORMAT_IS_YUV(fmt))
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return -EINVAL;
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dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true);
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dpu_hw_cdm_setup_cdwn(ctx, cdm);
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if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
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if (fmt->chroma_sample == DPU_CHROMA_H1V2)
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return -EINVAL; /*unsupported format */
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opmode = CDM_HDMI_PACK_OP_MODE_EN;
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opmode |= (fmt->chroma_sample << 1);
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}
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csc |= CDM_CSC10_OP_MODE_DST_FMT_YUV;
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csc &= ~CDM_CSC10_OP_MODE_SRC_FMT_YUV;
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csc |= CDM_CSC10_OP_MODE_EN;
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if (ctx && ctx->ops.bind_pingpong_blk)
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ctx->ops.bind_pingpong_blk(ctx, cdm->pp_id);
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DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);
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DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);
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return 0;
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}
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static void dpu_hw_cdm_bind_pingpong_blk(struct dpu_hw_cdm *ctx, const enum dpu_pingpong pp)
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{
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struct dpu_hw_blk_reg_map *c;
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int mux_cfg;
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c = &ctx->hw;
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mux_cfg = DPU_REG_READ(c, CDM_MUX);
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mux_cfg &= ~0xf;
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if (pp)
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mux_cfg |= (pp - PINGPONG_0) & 0x7;
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else
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mux_cfg |= 0xf;
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DPU_REG_WRITE(c, CDM_MUX, mux_cfg);
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}
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struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev,
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const struct dpu_cdm_cfg *cfg, void __iomem *addr,
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const struct dpu_mdss_version *mdss_rev)
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{
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struct dpu_hw_cdm *c;
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c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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c->hw.blk_addr = addr + cfg->base;
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c->hw.log_mask = DPU_DBG_MASK_CDM;
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/* Assign ops */
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c->idx = cfg->id;
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c->caps = cfg;
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c->ops.enable = dpu_hw_cdm_enable;
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if (mdss_rev->core_major_ver >= 5)
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c->ops.bind_pingpong_blk = dpu_hw_cdm_bind_pingpong_blk;
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return c;
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}
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