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3cc0bce86e
Add G7 package state residency counter in debugfs alongside existing G2,G6,G8,G10 states for complete power state visibility. Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com> Reviewed-by: Karthik Poosa <karthik.poosa@intel.com> Link: https://patch.msgid.link/20251016001219.37684-1-mohammed.thasleem@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
36 lines
1.0 KiB
C
36 lines
1.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_PMT_H_
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#define _XE_PMT_H_
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#include "xe_regs.h"
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#define BMG_PMT_BASE_OFFSET 0xDB000
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#define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE_OFFSET)
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#define PUNIT_TELEMETRY_GUID XE_REG(BMG_DISCOVERY_OFFSET + 0x4)
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#define BMG_ENERGY_STATUS_PMT_OFFSET (0x30)
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#define ENERGY_PKG REG_GENMASK64(31, 0)
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#define ENERGY_CARD REG_GENMASK64(63, 32)
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#define BMG_TELEMETRY_BASE_OFFSET 0xE0000
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#define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
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#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
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#define SG_REMAP_BITS REG_GENMASK(31, 24)
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#define BMG_MODS_RESIDENCY_OFFSET (0x4D0)
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#define BMG_G2_RESIDENCY_OFFSET (0x530)
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#define BMG_G6_RESIDENCY_OFFSET (0x538)
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#define BMG_G7_RESIDENCY_OFFSET (0x4B0)
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#define BMG_G8_RESIDENCY_OFFSET (0x540)
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#define BMG_G10_RESIDENCY_OFFSET (0x548)
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#define BMG_PCIE_LINK_L0_RESIDENCY_OFFSET (0x570)
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#define BMG_PCIE_LINK_L1_RESIDENCY_OFFSET (0x578)
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#define BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET (0x580)
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#endif
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