mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 06:44:00 -04:00
Merge tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Update dtc to upstream version v1.7.2-35-g52f07dcca47c
- Add stub for of_get_next_child_with_prefix()
- Convert of_msi_map_id() callers to of_msi_xlate()
DT bindings:
- Convert multiple text board bindings to DT schema format
- Add bindings for synaptics,synaptics_i2c touchscreen controller,
innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
vf610 reboot controller
- Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra
CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and
fsl,soc-operating-points properties for CPU nodes.
- Add QCom Glymur PDC and tegra264-agic interrupt controllers
- Add samsung,exynos8890-mali GPU to Arm Mali Midgard
- Drop Samsung S3C2410 display related bindings
- Allow separate DP lane and AUX connections in dp-connector
- Add some missing, undocumented vendor prefixes
- Add missing '#address-cells' properties in interrupt controller
bindings which dtc now warns about
- Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
bindings which are already covered by existing schemas.
- Various binding fixes for Mediatek platforms in mailbox, regulator,
pinctrl, timer, and display
- Drop work-around for yamllint quoting of values containing ','
- Various spelling, typo, grammar, and duplicated words fixes in DT
bindings and docs
- Add binding guidelines for defining properties at top level of
schemas, lack of node name ABI, and usage of simple-mfd"
* tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits)
dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
dt-bindings: gpu: Convert nvidia,gk20a to DT schema
dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
dt-bindings: vendor-prefixes: update regex for properties without a prefix
dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
scripts: dt_to_config: fix grammar and a typo in --help text
dt-bindings: fix spelling, typos, grammar, duplicated words
docs: dt: fix grammar and spelling
of: base: Add of_get_next_child_with_prefix() stub
dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
dt-bindings: soc: mediatek: pwrap: Add power-domains property
dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
dt-bindings: arm: mediatek: Support mt8183-audiosys variant
dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
dt-bindings: regulator: mediatek,mt6331: Add missing compatible
dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
...
This commit is contained in:
Linus Torvalds
@@ -4,7 +4,7 @@ rules:
|
||||
quoted-strings:
|
||||
required: only-when-needed
|
||||
extra-allowed:
|
||||
- '[$^,[]'
|
||||
- '[$^[]'
|
||||
- '^/$'
|
||||
line-length:
|
||||
# 80 chars should be enough, but don't fail if a line is longer
|
||||
|
||||
@@ -1,15 +0,0 @@
|
||||
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
|
||||
The EDAC accesses a range of registers in the SDRAM controller.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
|
||||
- altr,sdr-syscon : phandle of the sdr module
|
||||
- interrupts : Should contain the SDRAM ECC IRQ in the
|
||||
appropriate format for the IRQ controller.
|
||||
|
||||
Example:
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac";
|
||||
altr,sdr-syscon = <&sdr>;
|
||||
interrupts = <0 39 4>;
|
||||
};
|
||||
@@ -103,8 +103,9 @@ properties:
|
||||
- const: arm,juno-r2
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm AEMv8a Versatile Express Real-Time System Model
|
||||
(VE RTSM) is a programmers view of the Versatile Express with Arm
|
||||
- description: Arm AEMv8a (Architecture Envelope Model)
|
||||
Versatile Express Real-Time System Model (VE RTSM)
|
||||
is a programmers view of the Versatile Express with Arm
|
||||
v8A hardware. See ARM DUI 0575D.
|
||||
items:
|
||||
- const: arm,rtsm_ve,aemv8a
|
||||
@@ -139,7 +140,7 @@ patternProperties:
|
||||
the connection between the motherboard and any tiles. Sometimes the
|
||||
compatible is placed directly under this node, sometimes it is placed
|
||||
in a subnode named "motherboard-bus". Sometimes the compatible includes
|
||||
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
|
||||
"arm,vexpress,v2?-p1" sometimes (on software models) it is just
|
||||
"simple-bus". If the compatible is placed in the "motherboard-bus" node,
|
||||
it is stricter and always has two compatibles.
|
||||
type: object
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/cavium,thunder-88xx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cavium Thunder 88xx SoC
|
||||
|
||||
maintainers:
|
||||
- Robert Richter <rric@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- const: cavium,thunder-88xx
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,10 +0,0 @@
|
||||
Cavium Thunder platform device tree bindings
|
||||
--------------------------------------------
|
||||
|
||||
Boards with Cavium's Thunder SoC shall have following properties.
|
||||
|
||||
Root Node
|
||||
---------
|
||||
Required root node properties:
|
||||
|
||||
- compatible = "cavium,thunder-88xx";
|
||||
@@ -1,8 +0,0 @@
|
||||
Cavium ThunderX2 CN99XX platform tree bindings
|
||||
----------------------------------------------
|
||||
|
||||
Boards with Cavium ThunderX2 CN99XX SoC shall have the root property:
|
||||
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
|
||||
|
||||
These SoC uses the "cavium,thunder2" core which will be compatible
|
||||
with "brcm,vulcan".
|
||||
@@ -80,6 +80,8 @@ properties:
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- apm,potenza
|
||||
- apm,strega
|
||||
- apple,avalanche
|
||||
- apple,blizzard
|
||||
- apple,cyclone
|
||||
@@ -121,6 +123,10 @@ properties:
|
||||
- arm,arm1176jzf-s
|
||||
- arm,arm11mpcore
|
||||
- arm,armv8 # Only for s/w models
|
||||
- arm,c1-nano
|
||||
- arm,c1-premium
|
||||
- arm,c1-pro
|
||||
- arm,c1-ultra
|
||||
- arm,cortex-a5
|
||||
- arm,cortex-a7
|
||||
- arm,cortex-a8
|
||||
@@ -143,11 +149,14 @@ properties:
|
||||
- arm,cortex-a78
|
||||
- arm,cortex-a78ae
|
||||
- arm,cortex-a78c
|
||||
- arm,cortex-a320
|
||||
- arm,cortex-a510
|
||||
- arm,cortex-a520
|
||||
- arm,cortex-a520ae
|
||||
- arm,cortex-a710
|
||||
- arm,cortex-a715
|
||||
- arm,cortex-a720
|
||||
- arm,cortex-a720ae
|
||||
- arm,cortex-a725
|
||||
- arm,cortex-m0
|
||||
- arm,cortex-m0+
|
||||
@@ -345,10 +354,27 @@ properties:
|
||||
deprecated: true
|
||||
description: Use 'cpu-supply' instead
|
||||
|
||||
pu-supply:
|
||||
deprecated: true
|
||||
description: Only for i.MX6Q/DL/SL SoCs.
|
||||
|
||||
soc-supply:
|
||||
deprecated: true
|
||||
description: Only for i.MX6/7 Soc.
|
||||
|
||||
sram-supply:
|
||||
deprecated: true
|
||||
description: Use 'mem-supply' instead
|
||||
|
||||
fsl,soc-operating-points:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: FSL i.MX6 Soc operation-points when change cpu frequency
|
||||
deprecated: true
|
||||
items:
|
||||
items:
|
||||
- description: Frequency in kHz
|
||||
- description: Voltage for OPP in uV
|
||||
|
||||
mediatek,cci:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: Link to Mediatek Cache Coherent Interconnect
|
||||
|
||||
45
Documentation/devicetree/bindings/arm/marvell,berlin.yaml
Normal file
45
Documentation/devicetree/bindings/arm/marvell,berlin.yaml
Normal file
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell,berlin.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Synaptics/Marvell Berlin SoC
|
||||
|
||||
maintainers:
|
||||
- Jisheng Zhang <jszhang@kernel.org>
|
||||
|
||||
description:
|
||||
According to https://www.synaptics.com/company/news/conexant-marvell
|
||||
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
|
||||
Berlin SoCs are now Synaptics' SoCs.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sony,nsz-gs7
|
||||
- const: marvell,berlin2
|
||||
- const: marvell,berlin
|
||||
- items:
|
||||
- enum:
|
||||
- google,chromecast
|
||||
- valve,steamlink
|
||||
- const: marvell,berlin2cd
|
||||
- const: marvell,berlin
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,berlin2q-dmp
|
||||
- const: marvell,berlin2q
|
||||
- const: marvell,berlin
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,berlin4ct-dmp
|
||||
- marvell,berlin4ct-stb
|
||||
- const: marvell,berlin4ct
|
||||
- const: marvell,berlin
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,23 +0,0 @@
|
||||
Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
|
||||
----------------------------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
|
||||
shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp-98dx3236"
|
||||
|
||||
In addition, boards using the Marvell 98DX3336 SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp-98dx3336"
|
||||
|
||||
In addition, boards using the Marvell 98DX4251 SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp-98dx4251"
|
||||
@@ -115,45 +115,6 @@ ap_syscon: system-controller@6f4000 {
|
||||
SYSTEM CONTROLLER 1
|
||||
===================
|
||||
|
||||
Thermal:
|
||||
--------
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal*.yaml
|
||||
|
||||
The thermal IP can probe the temperature all around the processor. It
|
||||
may feature several channels, each of them wired to one sensor.
|
||||
|
||||
It is possible to setup an overheat interrupt by giving at least one
|
||||
critical point to any subnode of the thermal-zone node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
* marvell,armada-ap806-thermal
|
||||
- reg: register range associated with the thermal functions.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: overheat interrupt handle. Should point to line 18 of the
|
||||
SEI irqchip. See interrupt-controller/interrupts.txt
|
||||
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
|
||||
to this IP and represents the channel ID. There is one sensor per
|
||||
channel. O refers to the thermal IP internal channel, while positive
|
||||
IDs refer to each CPU.
|
||||
|
||||
Example:
|
||||
ap_syscon1: system-controller@6f8000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x6f8000 0x1000>;
|
||||
|
||||
ap_thermal: thermal-sensor@80 {
|
||||
compatible = "marvell,armada-ap806-thermal";
|
||||
reg = <0x80 0x10>;
|
||||
interrupt-parent = <&sei>;
|
||||
interrupts = <18>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Cluster clocks:
|
||||
---------------
|
||||
|
||||
|
||||
@@ -1,24 +0,0 @@
|
||||
Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
|
||||
---------------------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Armada 370 and Armada XP families
|
||||
shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada-370-xp"
|
||||
|
||||
In addition, boards using the Marvell Armada 370 SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada370"
|
||||
|
||||
In addition, boards using the Marvell Armada XP SoC shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armadaxp"
|
||||
|
||||
@@ -1,9 +0,0 @@
|
||||
Marvell Armada 375 Platforms Device Tree Bindings
|
||||
-------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Armada 375 family shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada375"
|
||||
@@ -1,31 +0,0 @@
|
||||
Marvell Armada 39x Platforms Device Tree Bindings
|
||||
-------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Armada 39x family shall have the
|
||||
following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
- compatible: must contain "marvell,armada390"
|
||||
|
||||
In addition, boards using the Marvell Armada 395 SoC shall have the
|
||||
following property before the common "marvell,armada390" one:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada395"
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390";
|
||||
|
||||
Boards using the Marvell Armada 398 SoC shall have the following
|
||||
property before the common "marvell,armada390" one:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,armada398"
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
|
||||
@@ -189,46 +189,3 @@ CP110_LABEL(syscon0): system-controller@440000 {
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
SYSTEM CONTROLLER 1
|
||||
===================
|
||||
|
||||
Thermal:
|
||||
--------
|
||||
|
||||
The thermal IP can probe the temperature all around the processor. It
|
||||
may feature several channels, each of them wired to one sensor.
|
||||
|
||||
It is possible to setup an overheat interrupt by giving at least one
|
||||
critical point to any subnode of the thermal-zone node.
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal*.yaml
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
* marvell,armada-cp110-thermal
|
||||
- reg: register range associated with the thermal functions.
|
||||
|
||||
Optional properties:
|
||||
- interrupts-extended: overheat interrupt handle. Should point to
|
||||
a line of the ICU-SEI irqchip (116 is what is usually used by the
|
||||
firmware). The ICU-SEI will redirect towards interrupt line #37 of the
|
||||
AP SEI which is shared across all CPs.
|
||||
See interrupt-controller/interrupts.txt
|
||||
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
|
||||
to this IP and represents the channel ID. There is one sensor per
|
||||
channel. O refers to the thermal IP internal channel.
|
||||
|
||||
Example:
|
||||
CP110_LABEL(syscon1): system-controller@6f8000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x6f8000 0x1000>;
|
||||
|
||||
CP110_LABEL(thermal): thermal-sensor@70 {
|
||||
compatible = "marvell,armada-cp110-thermal";
|
||||
reg = <0x70 0x10>;
|
||||
interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,27 +0,0 @@
|
||||
Marvell Kirkwood Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Kirkwood
|
||||
shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "marvell,kirkwood";
|
||||
|
||||
In order to support the kirkwood cpufreq driver, there must be a node
|
||||
cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
|
||||
where the "powersave" clock is a gating clock used to switch the CPU
|
||||
between the "cpu_clk" and the "ddrclk".
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-88SV131";
|
||||
clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
|
||||
clock-names = "cpu_clk", "ddrclk", "powersave";
|
||||
};
|
||||
@@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/marvell,armada-370-xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 370 and Armada XP platforms
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- ctera,c200-v2
|
||||
- dlink,dns327l
|
||||
- globalscale,mirabox
|
||||
- netgear,readynas-102
|
||||
- netgear,readynas-104
|
||||
- marvell,a370-db
|
||||
- marvell,a370-rd
|
||||
- seagate,dart-2
|
||||
- seagate,dart-4
|
||||
- seagate,cumulus-max
|
||||
- seagate,cumulus
|
||||
- synology,ds213j
|
||||
- const: marvell,armada370
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- mikrotik,crs305-1g-4s
|
||||
- mikrotik,crs326-24g-2s
|
||||
- mikrotik,crs328-4c-20s-4s
|
||||
- const: marvell,armadaxp-98dx3236
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
- items:
|
||||
- const: marvell,db-xc3-24g4xg
|
||||
- const: marvell,armadaxp-98dx3336
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
- items:
|
||||
- const: marvell,db-dxbc2
|
||||
- const: marvell,armadaxp-98dx4251
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,ix4-300d
|
||||
- linksys,mamba
|
||||
- marvell,rd-axpwifiap
|
||||
- netgear,readynas-2120
|
||||
- synology,ds414
|
||||
- const: marvell,armadaxp-mv78230
|
||||
- const: marvell,armadaxp
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
- items:
|
||||
- const: plathome,openblocks-ax3-4
|
||||
- const: marvell,armadaxp-mv78260
|
||||
- const: marvell,armadaxp
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,axp-db
|
||||
- marvell,axp-gp
|
||||
- marvell,axp-matrix
|
||||
- const: marvell,armadaxp-mv78460
|
||||
- const: marvell,armadaxp
|
||||
- const: marvell,armada-370-xp
|
||||
|
||||
additionalProperties: true
|
||||
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/marvell,armada375.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 375 Platform
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- const: marvell,a375-db
|
||||
- const: marvell,armada375
|
||||
|
||||
additionalProperties: true
|
||||
@@ -0,0 +1,32 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/marvell,armada390.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 39x Platforms
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: marvell,a390-db
|
||||
- const: marvell,armada390
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,a398-db
|
||||
- const: marvell,armada398
|
||||
- const: marvell,armada390
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,a395-gp
|
||||
- const: marvell,armada395
|
||||
- const: marvell,armada390
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,7 +0,0 @@
|
||||
Marvell Dove Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
Boards with a Marvell Dove SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
- compatible: must contain "marvell,dove";
|
||||
@@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/marvell,dove.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Dove SoC
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- compulab,cm-a510
|
||||
- solidrun,cubox
|
||||
- globalscale,d2plug
|
||||
- globalscale,d3plug
|
||||
- marvell,dove-db
|
||||
- const: marvell,dove
|
||||
- items:
|
||||
- const: solidrun,cubox-es
|
||||
- const: solidrun,cubox
|
||||
- const: marvell,dove
|
||||
- items:
|
||||
- const: compulab,sbc-a510
|
||||
- const: compulab,cm-a510
|
||||
- const: marvell,dove
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,105 +0,0 @@
|
||||
Marvell Kirkwood SoC Family Device Tree Bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Kirkwook family, eg 88f6281
|
||||
|
||||
* Required root node properties:
|
||||
compatible: must contain "marvell,kirkwood"
|
||||
|
||||
In addition, the above compatible shall be extended with the specific
|
||||
SoC. Currently known SoC compatibles are:
|
||||
|
||||
"marvell,kirkwood-88f6192"
|
||||
"marvell,kirkwood-88f6281"
|
||||
"marvell,kirkwood-88f6282"
|
||||
"marvell,kirkwood-88f6283"
|
||||
"marvell,kirkwood-88f6702"
|
||||
"marvell,kirkwood-98DX4122"
|
||||
|
||||
And in addition, the compatible shall be extended with the specific
|
||||
board. Currently known boards are:
|
||||
|
||||
"buffalo,linkstation-lsqvl"
|
||||
"buffalo,linkstation-lsvl"
|
||||
"buffalo,linkstation-lswsxl"
|
||||
"buffalo,linkstation-lswxl"
|
||||
"buffalo,linkstation-lswvl"
|
||||
"buffalo,lschlv2"
|
||||
"buffalo,lsxhl"
|
||||
"buffalo,lsxl"
|
||||
"cloudengines,pogo02"
|
||||
"cloudengines,pogoplugv4"
|
||||
"dlink,dns-320"
|
||||
"dlink,dns-320-a1"
|
||||
"dlink,dns-325"
|
||||
"dlink,dns-325-a1"
|
||||
"dlink,dns-kirkwood"
|
||||
"excito,b3"
|
||||
"globalscale,dreamplug-003-ds2001"
|
||||
"globalscale,guruplug"
|
||||
"globalscale,guruplug-server-plus"
|
||||
"globalscale,sheevaplug"
|
||||
"globalscale,sheevaplug"
|
||||
"globalscale,sheevaplug-esata"
|
||||
"globalscale,sheevaplug-esata-rev13"
|
||||
"iom,iconnect"
|
||||
"iom,iconnect-1.1"
|
||||
"iom,ix2-200"
|
||||
"keymile,km_kirkwood"
|
||||
"lacie,cloudbox"
|
||||
"lacie,inetspace_v2"
|
||||
"lacie,laplug"
|
||||
"lacie,nas2big"
|
||||
"lacie,netspace_lite_v2"
|
||||
"lacie,netspace_max_v2"
|
||||
"lacie,netspace_mini_v2"
|
||||
"lacie,netspace_v2"
|
||||
"marvell,db-88f6281-bp"
|
||||
"marvell,db-88f6282-bp"
|
||||
"marvell,mv88f6281gtw-ge"
|
||||
"marvell,rd88f6281"
|
||||
"marvell,rd88f6281"
|
||||
"marvell,rd88f6281-a0"
|
||||
"marvell,rd88f6281-a1"
|
||||
"mpl,cec4"
|
||||
"mpl,cec4-10"
|
||||
"netgear,readynas"
|
||||
"netgear,readynas"
|
||||
"netgear,readynas-duo-v2"
|
||||
"netgear,readynas-nv+-v2"
|
||||
"plathome,openblocks-a6"
|
||||
"plathome,openblocks-a7"
|
||||
"raidsonic,ib-nas6210"
|
||||
"raidsonic,ib-nas6210-b"
|
||||
"raidsonic,ib-nas6220"
|
||||
"raidsonic,ib-nas6220-b"
|
||||
"raidsonic,ib-nas62x0"
|
||||
"seagate,dockstar"
|
||||
"seagate,goflexnet"
|
||||
"synology,ds109"
|
||||
"synology,ds110jv10"
|
||||
"synology,ds110jv20"
|
||||
"synology,ds110jv30"
|
||||
"synology,ds111"
|
||||
"synology,ds209"
|
||||
"synology,ds210jv10"
|
||||
"synology,ds210jv20"
|
||||
"synology,ds212"
|
||||
"synology,ds212jv10"
|
||||
"synology,ds212jv20"
|
||||
"synology,ds212pv10"
|
||||
"synology,ds409"
|
||||
"synology,ds409slim"
|
||||
"synology,ds410j"
|
||||
"synology,ds411"
|
||||
"synology,ds411j"
|
||||
"synology,ds411slim"
|
||||
"synology,ds413jv10"
|
||||
"synology,rs212"
|
||||
"synology,rs409"
|
||||
"synology,rs411"
|
||||
"synology,rs812"
|
||||
"usi,topkick"
|
||||
"usi,topkick-1281P2"
|
||||
"zyxel,nsa310"
|
||||
"zyxel,nsa310a"
|
||||
@@ -0,0 +1,266 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/marvell,kirkwood.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Kirkwood SoC Family
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qnap,ts219
|
||||
- qnap,ts419
|
||||
- synology,ds110
|
||||
- synology,ds111
|
||||
- synology,ds209
|
||||
- synology,ds409slim
|
||||
- synology,ds411j
|
||||
- synology,ds411slim
|
||||
- synology,rs212
|
||||
- synology,rs409
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds109
|
||||
- const: synology,ds110jv20
|
||||
- const: synology,ds110
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds110jv10
|
||||
- const: synology,ds110jv30
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds210jv10
|
||||
- const: synology,ds210jv20
|
||||
- const: synology,ds210jv30
|
||||
- const: synology,ds211j
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds212jv10
|
||||
- const: synology,ds212jv20
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds212
|
||||
- const: synology,ds212pv10
|
||||
- const: synology,ds212pv10
|
||||
- const: synology,ds212pv20
|
||||
- const: synology,ds213airv10
|
||||
- const: synology,ds213v10
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds409
|
||||
- const: synology,ds410j
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,ds411
|
||||
- const: synology,ds413jv10
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: synology,rs411
|
||||
- const: synology,rs812
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- cloudengines,pogoplugv4
|
||||
- lacie,laplug
|
||||
- lacie,netspace_lite_v2
|
||||
- lacie,netspace_mini_v2
|
||||
- marvell,rd88f6192
|
||||
- seagate,blackarmor-nas220
|
||||
- enum:
|
||||
- marvell,kirkwood-88f6192
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- buffalo,lswsxl
|
||||
- buffalo,lswxl
|
||||
- checkpoint,l-50
|
||||
- cloudengines,pogoe02
|
||||
- ctera,c200-v1
|
||||
- dlink,dir-665
|
||||
- endian,4i-edge-200
|
||||
- excito,b3
|
||||
- globalscale,sheevaplug
|
||||
- hp,t5325
|
||||
- iom,ix2-200
|
||||
- lacie,inetspace_v2
|
||||
- lacie,netspace_v2
|
||||
- lacie,netspace_max_v2
|
||||
- marvell,db-88f6281-bp
|
||||
- marvell,mv88f6281gtw-ge
|
||||
- seagate,dockstar
|
||||
- seagate,goflexnet
|
||||
- zyxel,nsa310
|
||||
- zyxel,nsa320
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- buffalo,lschlv2
|
||||
- buffalo,lsxhl
|
||||
- const: buffalo,lsxl
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: dlink,dns-320-a1
|
||||
- const: dlink,dns-320
|
||||
- const: dlink,dns-kirkwood
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: dlink,dns-325-a1
|
||||
- const: dlink,dns-325
|
||||
- const: dlink,dns-kirkwood
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: globalscale,dreamplug-003-ds2001
|
||||
- const: globalscale,dreamplug
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: globalscale,guruplug-server-plus
|
||||
- const: globalscale,guruplug
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: globalscale,sheevaplug-esata-rev13
|
||||
- const: globalscale,sheevaplug-esata
|
||||
- const: globalscale,sheevaplug
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: iom,iconnect-1.1
|
||||
- const: iom,iconnect
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: lacie,d2net_v2
|
||||
- const: lacie,netxbig
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
- items:
|
||||
- enum:
|
||||
- lacie,net2big_v2
|
||||
- lacie,net5big_v2
|
||||
- const: lacie,netxbig
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,openrd-base
|
||||
- marvell,openrd-client
|
||||
- marvell,openrd-ultimate
|
||||
- const: marvell,openrd
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- marvell,rd88f6281-a
|
||||
- marvell,rd88f6281-z0
|
||||
- const: marvell,rd88f6281
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: mpl,cec4-10
|
||||
- const: mpl,cec4
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: raidsonic,ib-nas6210-b
|
||||
- const: raidsonic,ib-nas6220-b
|
||||
- const: raidsonic,ib-nas6210
|
||||
- const: raidsonic,ib-nas6220
|
||||
- const: raidsonic,ib-nas62x0
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: zyxel,nsa310a
|
||||
- const: zyxel,nsa310
|
||||
- const: marvell,kirkwood-88f6281
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- buffalo,lsqvl
|
||||
- buffalo,lsvl
|
||||
- buffalo,lswvl
|
||||
- linksys,viper
|
||||
- marvell,db-88f6282-bp
|
||||
- zyxel,nsa325
|
||||
- const: marvell,kirkwood-88f6282
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: lacie,nas2big
|
||||
- const: lacie,netxbig
|
||||
- const: marvell,kirkwood-88f6282
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- netgear,readynas-duo-v2
|
||||
- netgear,readynas-nv+-v2
|
||||
- const: netgear,readynas
|
||||
- const: marvell,kirkwood-88f6282
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- const: usi,topkick-1281P2
|
||||
- const: usi,topkick
|
||||
- const: marvell,kirkwood-88f6282
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- plathome,openblocks-a6
|
||||
- plathome,openblocks-a7
|
||||
- const: marvell,kirkwood-88f6283
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lacie,cloudbox
|
||||
- zyxel,nsa310s
|
||||
- const: marvell,kirkwood-88f6702
|
||||
- const: marvell,kirkwood
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- keymile,km_fixedeth
|
||||
- keymile,km_kirkwood
|
||||
- const: marvell,kirkwood-98DX4122
|
||||
- const: marvell,kirkwood
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,25 +0,0 @@
|
||||
Marvell Orion SoC Family Device Tree Bindings
|
||||
---------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Orion family, eg 88f5181
|
||||
|
||||
* Required root node properties:
|
||||
compatible: must contain "marvell,orion5x"
|
||||
|
||||
In addition, the above compatible shall be extended with the specific
|
||||
SoC. Currently known SoC compatibles are:
|
||||
|
||||
"marvell,orion5x-88f5181"
|
||||
"marvell,orion5x-88f5182"
|
||||
|
||||
And in addition, the compatible shall be extended with the specific
|
||||
board. Currently known boards are:
|
||||
|
||||
"buffalo,lsgl"
|
||||
"buffalo,lswsgl"
|
||||
"buffalo,lswtgl"
|
||||
"lacie,ethernet-disk-mini-v2"
|
||||
"lacie,d2-network"
|
||||
"marvell,rd-88f5182-nas"
|
||||
"maxtor,shared-storage-2"
|
||||
"netgear,wnr854t"
|
||||
@@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/marvell,orion5x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Orion5x SoC Family
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- netgear,wnr854t
|
||||
- const: marvell,orion5x-88f5181
|
||||
- const: marvell,orion5x
|
||||
- items:
|
||||
- enum:
|
||||
- buffalo,kurobox-pro
|
||||
- buffalo,lschl
|
||||
- buffalo,lsgl
|
||||
- buffalo,lswsgl
|
||||
- buffalo,lswtgl
|
||||
- lacie,ethernet-disk-mini-v2
|
||||
- lacie,d2-network
|
||||
- marvell,rd-88f5182-nas
|
||||
- maxtor,shared-storage-2
|
||||
- const: marvell,orion5x-88f5182
|
||||
- const: marvell,orion5x
|
||||
|
||||
additionalProperties: true
|
||||
@@ -23,6 +23,7 @@ properties:
|
||||
- mediatek,mt7622-audsys
|
||||
- mediatek,mt8167-audsys
|
||||
- mediatek,mt8173-audsys
|
||||
- mediatek,mt8183-audiosys
|
||||
- mediatek,mt8183-audsys
|
||||
- mediatek,mt8186-audsys
|
||||
- mediatek,mt8192-audsys
|
||||
@@ -41,13 +42,26 @@ properties:
|
||||
const: 1
|
||||
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-audiosys
|
||||
then:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
|
||||
else:
|
||||
properties:
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -28,6 +28,10 @@ properties:
|
||||
- arm,arm1136-pmu
|
||||
- arm,arm1176-pmu
|
||||
- arm,arm11mpcore-pmu
|
||||
- arm,c1-nano-pmu
|
||||
- arm,c1-premium-pmu
|
||||
- arm,c1-pro-pmu
|
||||
- arm,c1-ultra-pmu
|
||||
- arm,cortex-a5-pmu
|
||||
- arm,cortex-a7-pmu
|
||||
- arm,cortex-a8-pmu
|
||||
@@ -48,11 +52,14 @@ properties:
|
||||
- arm,cortex-a76-pmu
|
||||
- arm,cortex-a77-pmu
|
||||
- arm,cortex-a78-pmu
|
||||
- arm,cortex-a320-pmu
|
||||
- arm,cortex-a510-pmu
|
||||
- arm,cortex-a520-pmu
|
||||
- arm,cortex-a520ae-pmu
|
||||
- arm,cortex-a710-pmu
|
||||
- arm,cortex-a715-pmu
|
||||
- arm,cortex-a720-pmu
|
||||
- arm,cortex-a720ae-pmu
|
||||
- arm,cortex-a725-pmu
|
||||
- arm,cortex-x1-pmu
|
||||
- arm,cortex-x2-pmu
|
||||
|
||||
@@ -1,89 +0,0 @@
|
||||
Synaptics SoC Device Tree Bindings
|
||||
|
||||
According to https://www.synaptics.com/company/news/conexant-marvell
|
||||
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
|
||||
berlin SoCs are now Synaptics' SoCs now.
|
||||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
|
||||
shall have the following properties:
|
||||
|
||||
* Required root node properties:
|
||||
compatible: must contain "marvell,berlin"
|
||||
|
||||
In addition, the above compatible shall be extended with the specific
|
||||
SoC and board used. Currently known SoC compatibles are:
|
||||
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
|
||||
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
|
||||
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
|
||||
"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
|
||||
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
|
||||
|
||||
* Example:
|
||||
|
||||
/ {
|
||||
model = "Sony NSZ-GS7";
|
||||
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
|
||||
|
||||
...
|
||||
}
|
||||
|
||||
* Marvell Berlin CPU control bindings
|
||||
|
||||
CPU control register allows various operations on CPUs, like resetting them
|
||||
independently.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "marvell,berlin-cpu-ctrl"
|
||||
- reg: address and length of the register set
|
||||
|
||||
Example:
|
||||
|
||||
cpu-ctrl@f7dd0000 {
|
||||
compatible = "marvell,berlin-cpu-ctrl";
|
||||
reg = <0xf7dd0000 0x10000>;
|
||||
};
|
||||
|
||||
* Marvell Berlin2 chip control binding
|
||||
|
||||
Marvell Berlin SoCs have a chip control register set providing several
|
||||
individual registers dealing with pinmux, padmux, clock, reset, and secondary
|
||||
CPU boot address. Unfortunately, the individual registers are spread among the
|
||||
chip control registers, so there should be a single DT node only providing the
|
||||
different functions which are described below.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* the first and second values must be:
|
||||
"simple-mfd", "syscon"
|
||||
- reg: address and length of following register sets for
|
||||
BG2/BG2CD: chip control register set
|
||||
BG2Q: chip control register set and cpu pll registers
|
||||
|
||||
* Marvell Berlin2 system control binding
|
||||
|
||||
Marvell Berlin SoCs have a system control register set providing several
|
||||
individual registers dealing with pinmux, padmux, and reset.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* the first and second values must be:
|
||||
"simple-mfd", "syscon"
|
||||
- reg: address and length of the system control register set
|
||||
|
||||
Example:
|
||||
|
||||
chip: chip-control@ea0000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0xea0000 0x400>;
|
||||
|
||||
/* sub-device nodes */
|
||||
};
|
||||
|
||||
sysctrl: system-controller@d000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0xd000 0x100>;
|
||||
|
||||
/* sub-device nodes */
|
||||
};
|
||||
@@ -26,6 +26,9 @@ properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
||||
@@ -28,6 +28,7 @@ description: |
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/display/lvds-dual-ports.yaml#
|
||||
- $ref: /schemas/sound/dai-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -84,7 +84,10 @@ required:
|
||||
- interrupts
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: /schemas/sound/dai-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@@ -69,7 +69,10 @@ required:
|
||||
- vcc-supply
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: /schemas/sound/dai-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: GE B850v3 video bridge
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description: |
|
||||
STDP4028-ge-b850v3-fw bridges (LVDS-DP)
|
||||
STDP2690-ge-b850v3-fw bridges (DP-DP++)
|
||||
|
||||
The video processing pipeline on the second output on the GE B850v3:
|
||||
|
||||
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
|
||||
|
||||
Each bridge has a dedicated flash containing firmware for supporting the custom
|
||||
design. The result is that, in this design, neither the STDP4028 nor the
|
||||
STDP2690 behave as the stock bridges would. The compatible strings include the
|
||||
suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with
|
||||
the firmware specific for the GE B850v3.
|
||||
|
||||
The hardware do not provide control over the video processing pipeline, as the
|
||||
two bridges behaves as a single one. The only interfaces exposed by the
|
||||
hardware are EDID, HPD, and interrupts.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- megachips,stdp4028-ge-b850v3-fw
|
||||
- megachips,stdp2690-ge-b850v3-fw
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
properties:
|
||||
port@0:
|
||||
description: sink port
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
port@1:
|
||||
description: source port
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: megachips,stdp4028-ge-b850v3-fw
|
||||
then:
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@73 {
|
||||
compatible = "megachips,stdp4028-ge-b850v3-fw";
|
||||
reg = <0x73>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&stdp2690_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,91 +0,0 @@
|
||||
Drivers for the second video output of the GE B850v3:
|
||||
STDP4028-ge-b850v3-fw bridges (LVDS-DP)
|
||||
STDP2690-ge-b850v3-fw bridges (DP-DP++)
|
||||
|
||||
The video processing pipeline on the second output on the GE B850v3:
|
||||
|
||||
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
|
||||
|
||||
Each bridge has a dedicated flash containing firmware for supporting the custom
|
||||
design. The result is that, in this design, neither the STDP4028 nor the
|
||||
STDP2690 behave as the stock bridges would. The compatible strings include the
|
||||
suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with
|
||||
the firmware specific for the GE B850v3.
|
||||
|
||||
The hardware do not provide control over the video processing pipeline, as the
|
||||
two bridges behaves as a single one. The only interfaces exposed by the
|
||||
hardware are EDID, HPD, and interrupts.
|
||||
|
||||
stdp4028-ge-b850v3-fw required properties:
|
||||
- compatible : "megachips,stdp4028-ge-b850v3-fw"
|
||||
- reg : I2C bus address
|
||||
- interrupts : one interrupt should be described here, as in
|
||||
<0 IRQ_TYPE_LEVEL_HIGH>
|
||||
- ports : One input port(reg = <0>) and one output port(reg = <1>)
|
||||
|
||||
stdp2690-ge-b850v3-fw required properties:
|
||||
compatible : "megachips,stdp2690-ge-b850v3-fw"
|
||||
- reg : I2C bus address
|
||||
- ports : One input port(reg = <0>) and one output port(reg = <1>)
|
||||
|
||||
Example:
|
||||
|
||||
&mux2_i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
stdp4028@73 {
|
||||
compatible = "megachips,stdp4028-ge-b850v3-fw";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0x73>;
|
||||
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
stdp4028_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
stdp4028_out: endpoint {
|
||||
remote-endpoint = <&stdp2690_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stdp2690@72 {
|
||||
compatible = "megachips,stdp2690-ge-b850v3-fw";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0x72>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
stdp2690_in: endpoint {
|
||||
remote-endpoint = <&stdp4028_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
stdp2690_out: endpoint {
|
||||
/* Connector for external display */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -81,7 +81,10 @@ oneOf:
|
||||
- required:
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: /schemas/sound/dai-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@@ -109,7 +109,10 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: /schemas/sound/dai-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@@ -17,6 +17,7 @@ properties:
|
||||
# The reg property is required if and only if the device is connected
|
||||
# to an I2C bus. In pin strap mode, reg must not be specified.
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: I2C address of the device
|
||||
|
||||
# Pin 36 = Operation Enable / Reset Pin
|
||||
|
||||
@@ -31,10 +31,32 @@ properties:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Connection to controller providing DP signals
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: OF graph representation of signales routed to DP connector
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Connection to controller providing DP signals
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Connection to controller providing AUX signals
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- type
|
||||
- port
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- port
|
||||
- required:
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@@ -52,4 +74,32 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
/* DP connecttor being driven by the USB+DP combo PHY */
|
||||
connector {
|
||||
compatible = "dp-connector";
|
||||
label = "dp0";
|
||||
type = "full-size";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&phy_ss_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&phy_sbu_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
||||
@@ -46,7 +46,7 @@ properties:
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^panel@[0-3]$":
|
||||
"^(panel|bridge)@[0-3]$":
|
||||
description: Panels connected to the DSI link
|
||||
type: object
|
||||
|
||||
|
||||
@@ -102,6 +102,13 @@ properties:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: dpi
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -60,6 +60,18 @@ properties:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: describes how to locate the GCE client register
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle reference to a Mediatek GCE Mailbox
|
||||
- description:
|
||||
GCE subsys id mapping to a client defined in header
|
||||
include/dt-bindings/gce/<chip>-gce.h.
|
||||
- description: offset for the GCE register offset
|
||||
- description: size of the GCE register offset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -70,6 +82,7 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
@@ -79,5 +92,6 @@ examples:
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -64,6 +64,18 @@ properties:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: describes how to locate the GCE client register
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle reference to a Mediatek GCE Mailbox
|
||||
- description:
|
||||
GCE subsys id mapping to a client defined in header
|
||||
include/dt-bindings/gce/<chip>-gce.h.
|
||||
- description: offset for the GCE register offset
|
||||
- description: size of the GCE register offset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -77,7 +89,9 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@@ -88,5 +102,6 @@ examples:
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -178,6 +178,8 @@ properties:
|
||||
- innolux,g121xce-l01
|
||||
# InnoLux 15.6" FHD (1920x1080) TFT LCD panel
|
||||
- innolux,g156hce-l01
|
||||
# InnoLux 13.3" FHD (1920x1080) TFT LCD panel
|
||||
- innolux,n133hse-ea1
|
||||
# InnoLux 15.6" WXGA TFT LCD panel
|
||||
- innolux,n156bge-l21
|
||||
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
|
||||
@@ -228,6 +230,8 @@ properties:
|
||||
- netron-dy,e231732
|
||||
# Newhaven Display International 480 x 272 TFT LCD panel
|
||||
- newhaven,nhd-4.3-480272ef-atxl
|
||||
# NLT Technologies, Ltd. 12.1" WXGA (1280 x 800) LVDS TFT LCD panel
|
||||
- nlt,nl12880bc20-spwg-24
|
||||
# NLT Technologies, Ltd. 15.6" WXGA (1366×768) LVDS TFT LCD panel
|
||||
- nlt,nl13676bc25-03f
|
||||
# New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
|
||||
|
||||
@@ -97,9 +97,11 @@ allOf:
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
- if:
|
||||
|
||||
@@ -15,7 +15,6 @@ maintainers:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c2443-fimd
|
||||
- samsung,s3c6400-fimd
|
||||
- samsung,s5pv210-fimd
|
||||
- samsung,exynos3250-fimd
|
||||
|
||||
@@ -1,38 +0,0 @@
|
||||
OPA362 analog video amplifier
|
||||
|
||||
Required properties:
|
||||
- compatible: "ti,opa362"
|
||||
- enable-gpios: enable/disable output gpio
|
||||
|
||||
Required node:
|
||||
- Video port 0 for opa362 input
|
||||
- Video port 1 for opa362 output
|
||||
|
||||
Example:
|
||||
|
||||
tv_amp: opa362 {
|
||||
compatible = "ti,opa362";
|
||||
enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
opa_in: endpoint@0 {
|
||||
remote-endpoint = <&venc_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
opa_out: endpoint@0 {
|
||||
remote-endpoint = <&tv_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -53,6 +53,7 @@ properties:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- altr,sdram-edac
|
||||
- altr,sdram-edac-a10
|
||||
- altr,sdram-edac-s10
|
||||
|
||||
|
||||
203
Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml
Normal file
203
Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml
Normal file
@@ -0,0 +1,203 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/edac/apm,xgene-edac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene SoC EDAC
|
||||
|
||||
maintainers:
|
||||
- Khuong Dinh <khuong@os.amperecomputing.com>
|
||||
|
||||
description: >
|
||||
EDAC node is defined to describe on-chip error detection and correction.
|
||||
|
||||
The following error types are supported:
|
||||
|
||||
memory controller - Memory controller
|
||||
PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
|
||||
L3 - L3 cache controller
|
||||
SoC - SoC IPs such as Ethernet, SATA, etc
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: apm,xgene-edac
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: CPU bus (PCP) resource
|
||||
|
||||
'#address-cells':
|
||||
const: 2
|
||||
|
||||
'#size-cells':
|
||||
const: 2
|
||||
|
||||
ranges: true
|
||||
|
||||
interrupts:
|
||||
description: Interrupt-specifier for MCU, PMD, L3, or SoC error IRQ(s).
|
||||
items:
|
||||
- description: MCU error IRQ
|
||||
- description: PMD error IRQ
|
||||
- description: L3 error IRQ
|
||||
- description: SoC error IRQ
|
||||
minItems: 1
|
||||
|
||||
regmap-csw:
|
||||
description: Regmap of the CPU switch fabric (CSW) resource.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
regmap-mcba:
|
||||
description: Regmap of the MCB-A (memory bridge) resource.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
regmap-mcbb:
|
||||
description: Regmap of the MCB-B (memory bridge) resource.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
regmap-efuse:
|
||||
description: Regmap of the PMD efuse resource.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
regmap-rb:
|
||||
description: Regmap of the register bus resource (optional for compatibility).
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- regmap-csw
|
||||
- regmap-mcba
|
||||
- regmap-mcbb
|
||||
- regmap-efuse
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
# Child-node bindings
|
||||
patternProperties:
|
||||
'^edacmc@':
|
||||
description: Memory controller subnode
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: apm,xgene-edac-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
memory-controller:
|
||||
description: Instance number of the memory controller.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- memory-controller
|
||||
|
||||
|
||||
'^edacpmd@':
|
||||
description: PMD subnode
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: apm,xgene-edac-pmd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
pmd-controller:
|
||||
description: Instance number of the PMD controller.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- pmd-controller
|
||||
|
||||
'^edacl3@':
|
||||
description: L3 subnode
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- apm,xgene-edac-l3
|
||||
- apm,xgene-edac-l3-v2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
'^edacsoc@':
|
||||
description: SoC subnode
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- apm,xgene-edac-soc
|
||||
- apm,xgene-edac-soc-v1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
edac@78800000 {
|
||||
compatible = "apm,xgene-edac";
|
||||
reg = <0x0 0x78800000 0x0 0x100>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, <0x0 0x27 0x4>;
|
||||
|
||||
regmap-csw = <&csw>;
|
||||
regmap-mcba = <&mcba>;
|
||||
regmap-mcbb = <&mcbb>;
|
||||
regmap-efuse = <&efuse>;
|
||||
regmap-rb = <&rb>;
|
||||
|
||||
edacmc@7e800000 {
|
||||
compatible = "apm,xgene-edac-mc";
|
||||
reg = <0x0 0x7e800000 0x0 0x1000>;
|
||||
memory-controller = <0>;
|
||||
};
|
||||
|
||||
edacpmd@7c000000 {
|
||||
compatible = "apm,xgene-edac-pmd";
|
||||
reg = <0x0 0x7c000000 0x0 0x200000>;
|
||||
pmd-controller = <0>;
|
||||
};
|
||||
|
||||
edacl3@7e600000 {
|
||||
compatible = "apm,xgene-edac-l3";
|
||||
reg = <0x0 0x7e600000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
edacsoc@7e930000 {
|
||||
compatible = "apm,xgene-edac-soc-v1";
|
||||
reg = <0x0 0x7e930000 0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,112 +0,0 @@
|
||||
* APM X-Gene SoC EDAC node
|
||||
|
||||
EDAC node is defined to describe on-chip error detection and correction.
|
||||
The follow error types are supported:
|
||||
|
||||
memory controller - Memory controller
|
||||
PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
|
||||
L3 - L3 cache controller
|
||||
SoC - SoC IP's such as Ethernet, SATA, and etc
|
||||
|
||||
The following section describes the EDAC DT node binding.
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall be "apm,xgene-edac".
|
||||
- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
|
||||
- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
|
||||
- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
|
||||
- regmap-efuse : Regmap of the PMD efuse resource.
|
||||
- regmap-rb : Regmap of the register bus resource. This property
|
||||
is optional only for compatibility. If the RB
|
||||
error conditions are not cleared, it will
|
||||
continuously generate interrupt.
|
||||
- reg : First resource shall be the CPU bus (PCP) resource.
|
||||
- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
|
||||
IRQ(s).
|
||||
|
||||
Required properties for memory controller subnode:
|
||||
- compatible : Shall be "apm,xgene-edac-mc".
|
||||
- reg : First resource shall be the memory controller unit
|
||||
(MCU) resource.
|
||||
- memory-controller : Instance number of the memory controller.
|
||||
|
||||
Required properties for PMD subnode:
|
||||
- compatible : Shall be "apm,xgene-edac-pmd" or
|
||||
"apm,xgene-edac-pmd-v2".
|
||||
- reg : First resource shall be the PMD resource.
|
||||
- pmd-controller : Instance number of the PMD controller.
|
||||
|
||||
Required properties for L3 subnode:
|
||||
- compatible : Shall be "apm,xgene-edac-l3" or
|
||||
"apm,xgene-edac-l3-v2".
|
||||
- reg : First resource shall be the L3 EDAC resource.
|
||||
|
||||
Required properties for SoC subnode:
|
||||
- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
|
||||
"apm,xgene-edac-l3-soc" for general value reporting
|
||||
only.
|
||||
- reg : First resource shall be the SoC EDAC resource.
|
||||
|
||||
Example:
|
||||
csw: csw@7e200000 {
|
||||
compatible = "apm,xgene-csw", "syscon";
|
||||
reg = <0x0 0x7e200000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
mcba: mcba@7e700000 {
|
||||
compatible = "apm,xgene-mcb", "syscon";
|
||||
reg = <0x0 0x7e700000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
mcbb: mcbb@7e720000 {
|
||||
compatible = "apm,xgene-mcb", "syscon";
|
||||
reg = <0x0 0x7e720000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
efuse: efuse@1054a000 {
|
||||
compatible = "apm,xgene-efuse", "syscon";
|
||||
reg = <0x0 0x1054a000 0x0 0x20>;
|
||||
};
|
||||
|
||||
rb: rb@7e000000 {
|
||||
compatible = "apm,xgene-rb", "syscon";
|
||||
reg = <0x0 0x7e000000 0x0 0x10>;
|
||||
};
|
||||
|
||||
edac@78800000 {
|
||||
compatible = "apm,xgene-edac";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
regmap-csw = <&csw>;
|
||||
regmap-mcba = <&mcba>;
|
||||
regmap-mcbb = <&mcbb>;
|
||||
regmap-efuse = <&efuse>;
|
||||
regmap-rb = <&rb>;
|
||||
reg = <0x0 0x78800000 0x0 0x100>;
|
||||
interrupts = <0x0 0x20 0x4>,
|
||||
<0x0 0x21 0x4>,
|
||||
<0x0 0x27 0x4>;
|
||||
|
||||
edacmc@7e800000 {
|
||||
compatible = "apm,xgene-edac-mc";
|
||||
reg = <0x0 0x7e800000 0x0 0x1000>;
|
||||
memory-controller = <0>;
|
||||
};
|
||||
|
||||
edacpmd@7c000000 {
|
||||
compatible = "apm,xgene-edac-pmd";
|
||||
reg = <0x0 0x7c000000 0x0 0x200000>;
|
||||
pmd-controller = <0>;
|
||||
};
|
||||
|
||||
edacl3@7e600000 {
|
||||
compatible = "apm,xgene-edac-l3";
|
||||
reg = <0x0 0x7e600000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
edacsoc@7e930000 {
|
||||
compatible = "apm,xgene-edac-soc-v1";
|
||||
reg = <0x0 0x7e930000 0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Aspeed BMC SoC SDRAM EDAC controller
|
||||
|
||||
maintainers:
|
||||
- Stefan Schaeckeler <sschaeck@cisco.com>
|
||||
|
||||
description: >
|
||||
The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
|
||||
correction check).
|
||||
|
||||
The memory controller supports SECDED (single bit error correction, double bit
|
||||
error detection) and single bit error auto scrubbing by reserving 8 bits for
|
||||
every 64 bit word (effectively reducing available memory to 8/9).
|
||||
|
||||
Note, the bootloader must configure ECC mode in the memory controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-sdram-edac
|
||||
- aspeed,ast2500-sdram-edac
|
||||
- aspeed,ast2600-sdram-edac
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sdram@1e6e0000 {
|
||||
compatible = "aspeed,ast2500-sdram-edac";
|
||||
reg = <0x1e6e0000 0x174>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
@@ -1,28 +0,0 @@
|
||||
Aspeed BMC SoC EDAC node
|
||||
|
||||
The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
|
||||
correction check).
|
||||
|
||||
The memory controller supports SECDED (single bit error correction, double bit
|
||||
error detection) and single bit error auto scrubbing by reserving 8 bits for
|
||||
every 64 bit word (effectively reducing available memory to 8/9).
|
||||
|
||||
Note, the bootloader must configure ECC mode in the memory controller.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
- "aspeed,ast2400-sdram-edac"
|
||||
- "aspeed,ast2500-sdram-edac"
|
||||
- "aspeed,ast2600-sdram-edac"
|
||||
- reg: sdram controller register set should be <0x1e6e0000 0x174>
|
||||
- interrupts: should be AVIC interrupt #0
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
edac: sdram@1e6e0000 {
|
||||
compatible = "aspeed,ast2500-sdram-edac";
|
||||
reg = <0x1e6e0000 0x174>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
@@ -223,7 +223,7 @@ required:
|
||||
#
|
||||
# For multiple 'if' schema, group them under an 'allOf'.
|
||||
#
|
||||
# If the conditionals become too unweldy, then it may be better to just split
|
||||
# If the conditionals become too unwieldy, then it may be better to just split
|
||||
# the binding into separate schema documents.
|
||||
allOf:
|
||||
- if:
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fsi/aspeed,ast2400-cf-fsi-master.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASpeed ColdFire offloaded GPIO-based FSI master
|
||||
|
||||
maintainers:
|
||||
- Eddie James <eajames@linux.ibm.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/fsi/fsi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-cf-fsi-master
|
||||
- aspeed,ast2500-cf-fsi-master
|
||||
|
||||
clock-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO for FSI clock
|
||||
|
||||
data-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO for FSI data signal
|
||||
|
||||
enable-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO for enable signal
|
||||
|
||||
trans-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO for voltage translator enable
|
||||
|
||||
mux-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO for pin multiplexing with other functions (eg, external FSI masters)
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
Reference to the reserved memory for the ColdFire. Must be 2M aligned on
|
||||
AST2400 and 1M aligned on AST2500.
|
||||
|
||||
aspeed,cvic:
|
||||
description: Reference to the CVIC node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
aspeed,sram:
|
||||
description: Reference to the SRAM node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clock-gpios
|
||||
- data-gpios
|
||||
- enable-gpios
|
||||
- trans-gpios
|
||||
- mux-gpios
|
||||
- memory-region
|
||||
- aspeed,cvic
|
||||
- aspeed,sram
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
fsi-master {
|
||||
compatible = "aspeed,ast2500-cf-fsi-master";
|
||||
clock-gpios = <&gpio 0>;
|
||||
data-gpios = <&gpio 1>;
|
||||
enable-gpios = <&gpio 2>;
|
||||
trans-gpios = <&gpio 3>;
|
||||
mux-gpios = <&gpio 4>;
|
||||
memory-region = <&coldfire_memory>;
|
||||
aspeed,cvic = <&cvic>;
|
||||
aspeed,sram = <&sram>;
|
||||
};
|
||||
@@ -1,36 +0,0 @@
|
||||
Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
|
||||
------------------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible =
|
||||
"aspeed,ast2400-cf-fsi-master" for an AST2400 based system
|
||||
or
|
||||
"aspeed,ast2500-cf-fsi-master" for an AST2500 based system
|
||||
|
||||
- clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
|
||||
- data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
|
||||
- enable-gpios = <gpio-descriptor>; : GPIO for enable signal
|
||||
- trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
|
||||
- mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
|
||||
functions (eg, external FSI masters)
|
||||
- memory-region = <phandle>; : Reference to the reserved memory for
|
||||
the ColdFire. Must be 2M aligned on
|
||||
AST2400 and 1M aligned on AST2500
|
||||
- aspeed,sram = <phandle>; : Reference to the SRAM node.
|
||||
- aspeed,cvic = <phandle>; : Reference to the CVIC node.
|
||||
|
||||
Examples:
|
||||
|
||||
fsi-master {
|
||||
compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
|
||||
|
||||
clock-gpios = <&gpio 0>;
|
||||
data-gpios = <&gpio 1>;
|
||||
enable-gpios = <&gpio 2>;
|
||||
trans-gpios = <&gpio 3>;
|
||||
mux-gpios = <&gpio 4>;
|
||||
|
||||
memory-region = <&coldfire_memory>;
|
||||
aspeed,sram = <&sram>;
|
||||
aspeed,cvic = <&cvic>;
|
||||
}
|
||||
@@ -1,28 +0,0 @@
|
||||
Device-tree bindings for gpio-based FSI master driver
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible = "fsi-master-gpio";
|
||||
- clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
|
||||
- data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
|
||||
|
||||
Optional properties:
|
||||
- enable-gpios = <gpio-descriptor>; : GPIO for enable signal
|
||||
- trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
|
||||
- mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
|
||||
functions (eg, external FSI masters)
|
||||
- no-gpio-delays; : Don't add extra delays between GPIO
|
||||
accesses. This is useful when the HW
|
||||
GPIO block is running at a low enough
|
||||
frequency.
|
||||
|
||||
Examples:
|
||||
|
||||
fsi-master {
|
||||
compatible = "fsi-master-gpio", "fsi-master";
|
||||
clock-gpios = <&gpio 0>;
|
||||
data-gpios = <&gpio 1>;
|
||||
enable-gpios = <&gpio 2>;
|
||||
trans-gpios = <&gpio 3>;
|
||||
mux-gpios = <&gpio 4>;
|
||||
}
|
||||
63
Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml
Normal file
63
Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml
Normal file
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fsi/fsi-master-gpio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: fsi-master-gpio
|
||||
|
||||
maintainers:
|
||||
- Eddie James <eajames@linux.ibm.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/fsi/fsi-controller.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: fsi-master-gpio
|
||||
|
||||
clock-gpios:
|
||||
description: GPIO for FSI clock
|
||||
maxItems: 1
|
||||
|
||||
data-gpios:
|
||||
description: GPIO for FSI data signal
|
||||
maxItems: 1
|
||||
|
||||
enable-gpios:
|
||||
description: GPIO for enable signal
|
||||
maxItems: 1
|
||||
|
||||
trans-gpios:
|
||||
description: GPIO for voltage translator enable
|
||||
maxItems: 1
|
||||
|
||||
mux-gpios:
|
||||
description: GPIO for pin multiplexing with other functions (eg, external
|
||||
FSI masters)
|
||||
maxItems: 1
|
||||
|
||||
no-gpio-delays:
|
||||
description:
|
||||
Don't add extra delays between GPIO accesses. This is useful when the HW
|
||||
GPIO block is running at a low enough frequency.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clock-gpios
|
||||
- data-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
fsi-master {
|
||||
compatible = "fsi-master-gpio";
|
||||
clock-gpios = <&gpio 0>;
|
||||
data-gpios = <&gpio 1>;
|
||||
enable-gpios = <&gpio 2>;
|
||||
trans-gpios = <&gpio 3>;
|
||||
mux-gpios = <&gpio 4>;
|
||||
};
|
||||
@@ -1,6 +1,6 @@
|
||||
Android Goldfish QEMU Pipe
|
||||
|
||||
Andorid pipe virtual device generated by android emulator.
|
||||
Android pipe virtual device generated by android emulator.
|
||||
|
||||
Required properties:
|
||||
|
||||
|
||||
@@ -35,8 +35,8 @@ and bit-banged data signals:
|
||||
<&gpio1 15 0>;
|
||||
|
||||
In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
|
||||
a local offset to the GPIO line and the second cell represent consumer flags,
|
||||
such as if the consumer desire the line to be active low (inverted) or open
|
||||
a local offset to the GPIO line and the second cell represents consumer flags,
|
||||
such as if the consumer desires the line to be active low (inverted) or open
|
||||
drain. This is the recommended practice.
|
||||
|
||||
The exact meaning of each specifier cell is controller specific, and must be
|
||||
@@ -59,7 +59,7 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
|
||||
Optional standard bitfield specifiers for the last cell:
|
||||
|
||||
- Bit 0: 0 means active high, 1 means active low
|
||||
- Bit 1: 0 mean push-pull wiring, see:
|
||||
- Bit 1: 0 means push-pull wiring, see:
|
||||
https://en.wikipedia.org/wiki/Push-pull_output
|
||||
1 means single-ended wiring, see:
|
||||
https://en.wikipedia.org/wiki/Single-ended_triode
|
||||
@@ -176,7 +176,7 @@ example of a name from an SoC's reference manual) would not be desirable.
|
||||
|
||||
In either case placeholders are discouraged: rather use the "" (blank
|
||||
string) if the use of the GPIO line is undefined in your design. Ideally,
|
||||
try to add comments to the dts file describing the naming the convention
|
||||
try to add comments to the dts file describing the naming convention
|
||||
you have chosen, and specifying from where the names are derived.
|
||||
|
||||
The names are assigned starting from line offset 0, from left to right,
|
||||
@@ -304,7 +304,7 @@ pins 50..69.
|
||||
It is also possible to use pin groups for gpio ranges when pin groups are the
|
||||
easiest and most convenient mapping.
|
||||
|
||||
Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
|
||||
Both <pinctrl-base> and <count> must be set to 0 when using named pin groups
|
||||
names.
|
||||
|
||||
The property gpio-ranges-group-names must contain exactly one string for each
|
||||
@@ -313,7 +313,7 @@ range.
|
||||
Elements of gpio-ranges-group-names must contain the name of a pin group
|
||||
defined in the respective pin controller. The number of pins/GPIO lines in the
|
||||
range is the number of pins in that pin group. The number of pins of that
|
||||
group is defined int the implementation and not in the device tree.
|
||||
group is defined in the implementation and not in the device tree.
|
||||
|
||||
If numerical and named pin groups are mixed, the string corresponding to a
|
||||
numerical pin range in gpio-ranges-group-names must be empty.
|
||||
|
||||
@@ -53,8 +53,10 @@ properties:
|
||||
- enum:
|
||||
- rockchip,rk3399-mali
|
||||
- const: arm,mali-t860
|
||||
|
||||
# "arm,mali-t880"
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos8890-mali
|
||||
- const: arm,mali-t880
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/aspeed,ast2400-gfx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASPEED GFX Display Controller
|
||||
|
||||
maintainers:
|
||||
- Joel Stanley <joel@jms.id.au>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- aspeed,ast2400-gfx
|
||||
- aspeed,ast2500-gfx
|
||||
- aspeed,ast2600-gfx
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
a reserved-memory region to use for the framebuffer.
|
||||
|
||||
syscon:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: Phandle to SCU
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
- memory-region
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/aspeed-clock.h>
|
||||
|
||||
display@1e6e6000 {
|
||||
compatible = "aspeed,ast2500-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
|
||||
resets = <&syscon ASPEED_RESET_CRT1>;
|
||||
interrupts = <0x19>;
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
@@ -1,41 +0,0 @@
|
||||
Device tree configuration for the GFX display device on the ASPEED SoCs
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
* Must be one of the following:
|
||||
+ aspeed,ast2500-gfx
|
||||
+ aspeed,ast2400-gfx
|
||||
* In addition, the ASPEED pinctrl bindings require the 'syscon' property to
|
||||
be present
|
||||
|
||||
- reg: Physical base address and length of the GFX registers
|
||||
|
||||
- interrupts: interrupt number for the GFX device
|
||||
|
||||
- clocks: clock number used to generate the pixel clock
|
||||
|
||||
- resets: reset line that must be released to use the GFX device
|
||||
|
||||
- memory-region:
|
||||
Phandle to a memory region to allocate from, as defined in
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gfx: display@1e6e6000 {
|
||||
compatible = "aspeed,ast2500-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
|
||||
resets = <&syscon ASPEED_RESET_CRT1>;
|
||||
interrupts = <0x19>;
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
gfx_memory: framebuffer {
|
||||
size = <0x01000000>;
|
||||
alignment = <0x01000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
};
|
||||
@@ -1,115 +0,0 @@
|
||||
NVIDIA Tegra Graphics Processing Units
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,<gpu>"
|
||||
Currently recognized values:
|
||||
- nvidia,gk20a
|
||||
- nvidia,gm20b
|
||||
- nvidia,gp10b
|
||||
- nvidia,gv11b
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
Must contain two entries:
|
||||
- first entry for bar0
|
||||
- second entry for bar1
|
||||
- interrupts: Must contain an entry for each entry in interrupt-names.
|
||||
See ../interrupt-controller/interrupts.txt for details.
|
||||
- interrupt-names: Must include the following entries:
|
||||
- stall
|
||||
- nonstall
|
||||
- vdd-supply: regulator for supply voltage. Only required for GPUs not using
|
||||
power domains.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- gpu
|
||||
- pwr
|
||||
If the compatible string is "nvidia,gm20b", then the following clock
|
||||
is also required:
|
||||
- ref
|
||||
If the compatible string is "nvidia,gv11b", then the following clock is also
|
||||
required:
|
||||
- fuse
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- gpu
|
||||
- power-domains: GPUs that make use of power domains can define this property
|
||||
instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
|
||||
|
||||
Optional properties:
|
||||
- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
|
||||
|
||||
Example for GK20A:
|
||||
|
||||
gpu@57000000 {
|
||||
compatible = "nvidia,gk20a";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
vdd-supply = <&vdd_gpu>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_GPU>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
iommus = <&mc TEGRA_SWGROUP_GPU>;
|
||||
};
|
||||
|
||||
Example for GM20B:
|
||||
|
||||
gpu@57000000 {
|
||||
compatible = "nvidia,gm20b";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
clocks = <&tegra_car TEGRA210_CLK_GPU>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_G_REF>;
|
||||
clock-names = "gpu", "pwr", "ref";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
iommus = <&mc TEGRA_SWGROUP_GPU>;
|
||||
};
|
||||
|
||||
Example for GP10B:
|
||||
|
||||
gpu@17000000 {
|
||||
compatible = "nvidia,gp10b";
|
||||
reg = <0x0 0x17000000 0x0 0x1000000>,
|
||||
<0x0 0x18000000 0x0 0x1000000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
|
||||
<&bpmp TEGRA186_CLK_GPU>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&bpmp TEGRA186_RESET_GPU>;
|
||||
reset-names = "gpu";
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
|
||||
iommus = <&smmu TEGRA186_SID_GPU>;
|
||||
};
|
||||
|
||||
Example for GV11B:
|
||||
|
||||
gpu@17000000 {
|
||||
compatible = "nvidia,gv11b";
|
||||
reg = <0x17000000 0x1000000>,
|
||||
<0x18000000 0x1000000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
|
||||
<&bpmp TEGRA194_CLK_GPU_PWR>,
|
||||
<&bpmp TEGRA194_CLK_FUSE>;
|
||||
clock-names = "gpu", "pwr", "fuse";
|
||||
resets = <&bpmp TEGRA194_RESET_GPU>;
|
||||
reset-names = "gpu";
|
||||
dma-coherent;
|
||||
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
|
||||
iommus = <&smmu TEGRA194_SID_GPU>;
|
||||
};
|
||||
171
Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
Normal file
171
Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
Normal file
@@ -0,0 +1,171 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Graphics Processing Units
|
||||
|
||||
maintainers:
|
||||
- Alexandre Courbot <acourbot@nvidia.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <treding@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,gk20a
|
||||
- nvidia,gm20b
|
||||
- nvidia,gp10b
|
||||
- nvidia,gv11b
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Bar0 register window
|
||||
- description: Bar1 register window
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Stall interrupt
|
||||
- description: Nonstall interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: stall
|
||||
- const: nonstall
|
||||
|
||||
vdd-supply:
|
||||
description:
|
||||
Regulator for GPU supply voltage
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: GPU clock
|
||||
- description: Power clock
|
||||
- description: Reference or fuse clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: gpu
|
||||
- const: pwr
|
||||
- enum: [ ref, fuse ]
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: gpu
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
minItems: 4
|
||||
maxItems: 12
|
||||
|
||||
interconnect-names:
|
||||
minItems: 4
|
||||
maxItems: 12
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,gp10b
|
||||
- nvidia,gv11b
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
else:
|
||||
properties:
|
||||
interconnects: false
|
||||
interconnect-names: false
|
||||
|
||||
required:
|
||||
- vdd-supply
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,gp10b
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
maxItems: 4
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write-0
|
||||
- const: read-1
|
||||
- const: write-1
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,gv11b
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
minItems: 12
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: read-0-hp
|
||||
- const: write-0
|
||||
- const: read-1
|
||||
- const: read-1-hp
|
||||
- const: write-1
|
||||
- const: read-2
|
||||
- const: read-2-hp
|
||||
- const: write-2
|
||||
- const: read-3
|
||||
- const: read-3-hp
|
||||
- const: write-3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/tegra124-car-common.h>
|
||||
#include <dt-bindings/memory/tegra124-mc.h>
|
||||
|
||||
gpu@57000000 {
|
||||
compatible = "nvidia,gk20a";
|
||||
reg = <0x57000000 0x01000000>,
|
||||
<0x58000000 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
vdd-supply = <&vdd_gpu>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_GPU>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
iommus = <&mc TEGRA_SWGROUP_GPU>;
|
||||
};
|
||||
@@ -59,6 +59,7 @@ properties:
|
||||
- nvidia,tegra186-agic
|
||||
- nvidia,tegra194-agic
|
||||
- nvidia,tegra234-agic
|
||||
- nvidia,tegra264-agic
|
||||
- const: nvidia,tegra210-agic
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
@@ -36,12 +36,27 @@ properties:
|
||||
const: 0
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
description:
|
||||
A value of 4 means that interrupt specifiers contain the interrupt-type or
|
||||
type-specific information cells.
|
||||
enum: [ 2, 4 ]
|
||||
|
||||
pic-no-reset:
|
||||
description: Indicates the PIC shall not be reset during runtime initialization.
|
||||
type: boolean
|
||||
|
||||
single-cpu-affinity:
|
||||
description:
|
||||
If present, non-IPI interrupts will be routed to a single CPU at a time.
|
||||
type: boolean
|
||||
|
||||
last-interrupt-source:
|
||||
description:
|
||||
Some MPICs do not correctly report the number of hardware sources in the
|
||||
global feature registers. This value, if specified, overrides the value
|
||||
read from MPIC_GREG_FEATURE_LAST_SRC.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -1,84 +0,0 @@
|
||||
Hisilicon mbigen device tree bindings.
|
||||
=======================================
|
||||
|
||||
Mbigen means: message based interrupt generator.
|
||||
|
||||
MBI is kind of msi interrupt only used on Non-PCI devices.
|
||||
|
||||
To reduce the wired interrupt number connected to GIC,
|
||||
Hisilicon designed mbigen to collect and generate interrupt.
|
||||
|
||||
|
||||
Non-pci devices can connect to mbigen and generate the
|
||||
interrupt by writing ITS register.
|
||||
|
||||
The mbigen chip and devices connect to mbigen have the following properties:
|
||||
|
||||
Mbigen main node required properties:
|
||||
-------------------------------------------
|
||||
- compatible: Should be "hisilicon,mbigen-v2"
|
||||
|
||||
- reg: Specifies the base physical address and size of the Mbigen
|
||||
registers.
|
||||
|
||||
Mbigen sub node required properties:
|
||||
------------------------------------------
|
||||
- interrupt controller: Identifies the node as an interrupt controller
|
||||
|
||||
- msi-parent: Specifies the MSI controller this mbigen use.
|
||||
For more detail information,please refer to the generic msi-parent binding in
|
||||
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
|
||||
|
||||
- num-pins: the total number of pins implemented in this Mbigen
|
||||
instance.
|
||||
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 2.
|
||||
|
||||
The 1st cell is hardware pin number of the interrupt.This number is local to
|
||||
each mbigen chip and in the range from 0 to the maximum interrupts number
|
||||
of the mbigen.
|
||||
|
||||
The 2nd cell is the interrupt trigger type.
|
||||
The value of this cell should be:
|
||||
1: rising edge triggered
|
||||
or
|
||||
4: high level triggered
|
||||
|
||||
Examples:
|
||||
|
||||
mbigen_chip_dsa {
|
||||
compatible = "hisilicon,mbigen-v2";
|
||||
reg = <0x0 0xc0080000 0x0 0x10000>;
|
||||
|
||||
mbigen_gmac:intc_gmac {
|
||||
interrupt-controller;
|
||||
msi-parent = <&its_dsa 0x40b1c>;
|
||||
num-pins = <9>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
mbigen_i2c:intc_i2c {
|
||||
interrupt-controller;
|
||||
msi-parent = <&its_dsa 0x40b0e>;
|
||||
num-pins = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
Devices connect to mbigen required properties:
|
||||
----------------------------------------------------
|
||||
-interrupts:Specifies the interrupt source.
|
||||
For the specific information of each cell in this property,please refer to
|
||||
the "interrupt-cells" description mentioned above.
|
||||
|
||||
Examples:
|
||||
gmac0: ethernet@c2080000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0xc2080000 0 0x20000>,
|
||||
<0 0xc0000000 0 0x1000>;
|
||||
interrupt-parent = <&mbigen_device_gmac>;
|
||||
interrupts = <656 1>,
|
||||
<657 1>;
|
||||
};
|
||||
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/hisilicon,mbigen-v2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Hisilicon mbigen v2
|
||||
|
||||
maintainers:
|
||||
- Wei Xu <xuwei5@hisilicon.com>
|
||||
|
||||
description: >
|
||||
Mbigen means: message based interrupt generator.
|
||||
|
||||
MBI is kind of msi interrupt only used on Non-PCI devices.
|
||||
|
||||
To reduce the wired interrupt number connected to GIC, Hisilicon designed
|
||||
mbigen to collect and generate interrupt.
|
||||
|
||||
Non-pci devices can connect to mbigen and generate the interrupt by writing
|
||||
ITS register.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: hisilicon,mbigen-v2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
num-pins:
|
||||
description: The total number of pins implemented in this Mbigen instance.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- msi-parent
|
||||
- num-pins
|
||||
|
||||
examples:
|
||||
- |
|
||||
mbigen@c0080000 {
|
||||
compatible = "hisilicon,mbigen-v2";
|
||||
reg = <0xc0080000 0x10000>;
|
||||
|
||||
mbigen_gmac: intc_gmac {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
msi-parent = <&its_dsa 0x40b1c>;
|
||||
num-pins = <9>;
|
||||
};
|
||||
|
||||
mbigen_i2c: intc_i2c {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
msi-parent = <&its_dsa 0x40b0e>;
|
||||
num-pins = <2>;
|
||||
};
|
||||
};
|
||||
@@ -49,6 +49,9 @@ patternProperties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
|
||||
@@ -26,6 +26,7 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,glymur-pdc
|
||||
- qcom,qcs615-pdc
|
||||
- qcom,qcs8300-pdc
|
||||
- qcom,qdu1000-pdc
|
||||
|
||||
@@ -52,7 +52,7 @@ description: |+
|
||||
As above, The Multimedia HW will go through SMI and M4U while it
|
||||
access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
|
||||
smi local arbiter and smi common. It will control whether the Multimedia
|
||||
HW should go though the m4u for translation or bypass it and talk
|
||||
HW should go through the m4u for translation or bypass it and talk
|
||||
directly with EMI. And also SMI help control the power domain and clocks for
|
||||
each local arbiter.
|
||||
|
||||
|
||||
@@ -62,7 +62,7 @@ properties:
|
||||
default-state:
|
||||
description:
|
||||
The initial state of the LED. If the LED is already on or off and the
|
||||
default-state property is set the to same value, then no glitch should be
|
||||
default-state property is set to the same value, then no glitch should be
|
||||
produced where the LED momentarily turns off (or on). The "keep" setting
|
||||
will keep the LED at whatever its current state is, without producing a
|
||||
glitch.
|
||||
|
||||
@@ -1,59 +0,0 @@
|
||||
Broadcom FlexRM Ring Manager
|
||||
============================
|
||||
The Broadcom FlexRM ring manager provides a set of rings which can be
|
||||
used to submit work to offload engines. An SoC may have multiple FlexRM
|
||||
hardware blocks. There is one device tree entry per FlexRM block. The
|
||||
FlexRM driver will create a mailbox-controller instance for given FlexRM
|
||||
hardware block where each mailbox channel is a separate FlexRM ring.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Should be "brcm,iproc-flexrm-mbox"
|
||||
- reg: Specifies base physical address and size of the FlexRM
|
||||
ring registers
|
||||
- msi-parent: Phandles (and potential Device IDs) to MSI controllers
|
||||
The FlexRM engine will send MSIs (instead of wired
|
||||
interrupts) to CPU. There is one MSI for each FlexRM ring.
|
||||
Refer devicetree/bindings/interrupt-controller/msi.txt
|
||||
- #mbox-cells: Specifies the number of cells needed to encode a mailbox
|
||||
channel. This should be 3.
|
||||
|
||||
The 1st cell is the mailbox channel number.
|
||||
|
||||
The 2nd cell contains MSI completion threshold. This is the
|
||||
number of completion messages for which FlexRM will inject
|
||||
one MSI interrupt to CPU.
|
||||
|
||||
The 3rd cell contains MSI timer value representing time for
|
||||
which FlexRM will wait to accumulate N completion messages
|
||||
where N is the value specified by 2nd cell above. If FlexRM
|
||||
does not get required number of completion messages in time
|
||||
specified by this cell then it will inject one MSI interrupt
|
||||
to CPU provided at least one completion message is available.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- dma-coherent: Present if DMA operations made by the FlexRM engine (such
|
||||
as DMA descriptor access, access to buffers pointed by DMA
|
||||
descriptors and read/write pointer updates to DDR) are
|
||||
cache coherent with the CPU.
|
||||
|
||||
Example:
|
||||
--------
|
||||
crypto_mbox: mbox@67000000 {
|
||||
compatible = "brcm,iproc-flexrm-mbox";
|
||||
reg = <0x67000000 0x200000>;
|
||||
msi-parent = <&gic_its 0x7f00>;
|
||||
#mbox-cells = <3>;
|
||||
};
|
||||
|
||||
crypto@672c0000 {
|
||||
compatible = "brcm,spu2-v2-crypto";
|
||||
reg = <0x672c0000 0x1000>;
|
||||
mboxes = <&crypto_mbox 0 0x1 0xffff>,
|
||||
<&crypto_mbox 1 0x1 0xffff>,
|
||||
<&crypto_mbox 16 0x1 0xffff>,
|
||||
<&crypto_mbox 17 0x1 0xffff>,
|
||||
<&crypto_mbox 30 0x1 0xffff>,
|
||||
<&crypto_mbox 31 0x1 0xffff>;
|
||||
};
|
||||
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/brcm,iproc-flexrm-mbox.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom FlexRM Ring Manager
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
description:
|
||||
The Broadcom FlexRM ring manager provides a set of rings which can be used to
|
||||
submit work to offload engines. An SoC may have multiple FlexRM hardware
|
||||
blocks. There is one device tree entry per FlexRM block. The FlexRM driver
|
||||
will create a mailbox-controller instance for given FlexRM hardware block
|
||||
where each mailbox channel is a separate FlexRM ring.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,iproc-flexrm-mbox
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
'#mbox-cells':
|
||||
description: >
|
||||
The 1st cell is the mailbox channel number.
|
||||
|
||||
The 2nd cell contains MSI completion threshold. This is the number of
|
||||
completion messages for which FlexRM will inject one MSI interrupt to CPU.
|
||||
|
||||
The 3rd cell contains MSI timer value representing time for which FlexRM
|
||||
will wait to accumulate N completion messages where N is the value
|
||||
specified by 2nd cell above. If FlexRM does not get required number of
|
||||
completion messages in time specified by this cell then it will inject one
|
||||
MSI interrupt to CPU provided at least one completion message is
|
||||
available.
|
||||
const: 3
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- msi-parent
|
||||
- '#mbox-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mailbox@67000000 {
|
||||
compatible = "brcm,iproc-flexrm-mbox";
|
||||
reg = <0x67000000 0x200000>;
|
||||
msi-parent = <&gic_its 0x7f00>;
|
||||
#mbox-cells = <3>;
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -1,25 +0,0 @@
|
||||
The PDC driver manages data transfer to and from various offload engines
|
||||
on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is
|
||||
one device tree entry per block. On some chips, the PDC functionality is
|
||||
handled by the FA2 (Northstar Plus).
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for
|
||||
FA2/Northstar Plus.
|
||||
- reg: Should contain PDC registers location and length.
|
||||
- interrupts: Should contain the IRQ line for the PDC.
|
||||
- #mbox-cells: 1
|
||||
- brcm,rx-status-len: Length of metadata preceding received frames, in bytes.
|
||||
|
||||
Optional properties:
|
||||
- brcm,use-bcm-hdr: present if a BCM header precedes each frame.
|
||||
|
||||
Example:
|
||||
pdc0: iproc-pdc0@612c0000 {
|
||||
compatible = "brcm,iproc-pdc-mbox";
|
||||
reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>; /* one cell per mailbox channel */
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
||||
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/brcm,iproc-pdc-mbox.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom iProc PDC mailbox
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
description:
|
||||
The PDC driver manages data transfer to and from various offload engines on
|
||||
some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is one
|
||||
device tree entry per block. On some chips, the PDC functionality is handled
|
||||
by the FA2 (Northstar Plus).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,iproc-pdc-mbox
|
||||
- brcm,iproc-fa2-mbox
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#mbox-cells':
|
||||
const: 1
|
||||
|
||||
brcm,rx-status-len:
|
||||
description:
|
||||
Length of metadata preceding received frames, in bytes.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
brcm,use-bcm-hdr:
|
||||
type: boolean
|
||||
description:
|
||||
Present if a BCM header precedes each frame.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#mbox-cells'
|
||||
- brcm,rx-status-len
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mailbox0@612c0000 {
|
||||
compatible = "brcm,iproc-pdc-mbox";
|
||||
reg = <0x612c0000 0x445>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
||||
@@ -1,16 +0,0 @@
|
||||
* rWTM BIU Mailbox driver for Armada 37xx
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "marvell,armada-3700-rwtm-mailbox"
|
||||
- reg: physical base address of the mailbox and length of memory mapped
|
||||
region
|
||||
- interrupts: the IRQ line for the mailbox
|
||||
- #mbox-cells: must be 1
|
||||
|
||||
Example:
|
||||
rwtm: mailbox@b0000 {
|
||||
compatible = "marvell,armada-3700-rwtm-mailbox";
|
||||
reg = <0xb0000 0x100>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/marvell,armada-3700-rwtm-mailbox.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 3700 rWTM Mailbox
|
||||
|
||||
maintainers:
|
||||
- Marek Behún <kabel@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,armada-3700-rwtm-mailbox
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#mbox-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#mbox-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mailbox@b0000 {
|
||||
compatible = "marvell,armada-3700-rwtm-mailbox";
|
||||
reg = <0xb0000 0x100>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
@@ -60,17 +60,6 @@ required:
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8195-gce
|
||||
then:
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/rockchip,rk3368-mailbox.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3368 Mailbox Controller
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description:
|
||||
The Rockchip mailbox is used by the Rockchip CPU cores to communicate
|
||||
requests to MCU processor.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rockchip,rk3368-mailbox
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: pclk_mailbox
|
||||
|
||||
interrupts:
|
||||
description: One interrupt for each channel
|
||||
maxItems: 4
|
||||
|
||||
'#mbox-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#mbox-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mailbox@ff6b0000 {
|
||||
compatible = "rockchip,rk3368-mailbox";
|
||||
reg = <0xff6b0000 0x1000>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
@@ -1,32 +0,0 @@
|
||||
Rockchip mailbox
|
||||
|
||||
The Rockchip mailbox is used by the Rockchip CPU cores to communicate
|
||||
requests to MCU processor.
|
||||
|
||||
Refer to ./mailbox.txt for generic information about mailbox device-tree
|
||||
bindings.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "rockchip,rk3368-mbox" for rk3368
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: The interrupt number to the cpu. The interrupt specifier format
|
||||
depends on the interrupt controller.
|
||||
- #mbox-cells: Common mailbox binding property to identify the number
|
||||
of cells required for the mailbox specifier. Should be 1
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
/* RK3368 */
|
||||
mbox: mbox@ff6b0000 {
|
||||
compatible = "rockchip,rk3368-mailbox";
|
||||
reg = <0x0 0xff6b0000 0x0 0x1000>,
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mt8173-vpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek MT8173 Video Processor Unit
|
||||
|
||||
maintainers:
|
||||
- Ariel D'Alessandro <ariel.dalessandro@collabora.com>
|
||||
|
||||
description:
|
||||
Video Processor Unit is a HW video controller. It controls HW Codec including
|
||||
H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color
|
||||
convert).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8173-vpu
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: tcm
|
||||
- const: cfg_reg
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: main
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- memory-region
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
vpu: vpu@10020000 {
|
||||
compatible = "mediatek,mt8173-vpu";
|
||||
reg = <0 0x10020000 0 0x30000>,
|
||||
<0 0x10050000 0 0x100>;
|
||||
reg-names = "tcm", "cfg_reg";
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_SCP_SEL>;
|
||||
clock-names = "main";
|
||||
memory-region = <&vpu_dma_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -5,7 +5,8 @@ Media Data Path is used for scaling and color space conversion.
|
||||
Required properties (controller node):
|
||||
- compatible: "mediatek,mt8173-mdp"
|
||||
- mediatek,vpu: the node of video processor unit, see
|
||||
Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
|
||||
Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml for
|
||||
details.
|
||||
|
||||
Required properties (all function blocks, child node):
|
||||
- compatible: Should be one of
|
||||
|
||||
@@ -1,31 +0,0 @@
|
||||
* Mediatek Video Processor Unit
|
||||
|
||||
Video Processor Unit is a HW video controller. It controls HW Codec including
|
||||
H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,mt8173-vpu"
|
||||
- reg: Must contain an entry for each entry in reg-names.
|
||||
- reg-names: Must include the following entries:
|
||||
"tcm": tcm base
|
||||
"cfg_reg": Main configuration registers base
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- clocks : clock name from clock manager
|
||||
- clock-names: must be main. It is the main clock of VPU
|
||||
|
||||
Optional properties:
|
||||
- memory-region: phandle to a node describing memory (see
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
|
||||
to be used for VPU extended memory; if not present, VPU may be located
|
||||
anywhere in the memory
|
||||
|
||||
Example:
|
||||
vpu: vpu@10020000 {
|
||||
compatible = "mediatek,mt8173-vpu";
|
||||
reg = <0 0x10020000 0 0x30000>,
|
||||
<0 0x10050000 0 0x100>;
|
||||
reg-names = "tcm", "cfg_reg";
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen TOP_SCP_SEL>;
|
||||
clock-names = "main";
|
||||
};
|
||||
@@ -1,17 +0,0 @@
|
||||
* Device tree bindings for Aspeed SoC Display Controller (GFX)
|
||||
|
||||
The Aspeed SoC Display Controller primarily does as its name suggests, but also
|
||||
participates in pinmux requests on the g5 SoCs. It is therefore considered a
|
||||
syscon device.
|
||||
|
||||
Required properties:
|
||||
- compatible: "aspeed,ast2500-gfx", "syscon"
|
||||
- reg: contains offset/length value of the GFX memory
|
||||
region.
|
||||
|
||||
Example:
|
||||
|
||||
gfx: display@1e6e6000 {
|
||||
compatible = "aspeed,ast2500-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
};
|
||||
@@ -26,7 +26,7 @@ properties:
|
||||
'#gpio-cells':
|
||||
description:
|
||||
The first cell is the pin number.
|
||||
The second cell is is used to specify flags.
|
||||
The second cell is used to specify flags.
|
||||
See ../gpio/gpio.txt for more information.
|
||||
const: 2
|
||||
|
||||
|
||||
@@ -26,7 +26,7 @@ properties:
|
||||
'#gpio-cells':
|
||||
description:
|
||||
The first cell is the pin number.
|
||||
The second cell is is used to specify flags.
|
||||
The second cell is used to specify flags.
|
||||
See ../gpio/gpio.txt for more information.
|
||||
const: 2
|
||||
|
||||
|
||||
@@ -28,7 +28,7 @@ properties:
|
||||
'#gpio-cells':
|
||||
description:
|
||||
The first cell is the pin number.
|
||||
The second cell is is used to specify flags.
|
||||
The second cell is used to specify flags.
|
||||
See ../gpio/gpio.txt for more information.
|
||||
const: 2
|
||||
|
||||
|
||||
@@ -57,7 +57,7 @@ properties:
|
||||
# latter case. We choose to use the XOR logic for GPIO CD and WP
|
||||
# lines. This means, the two properties are "superimposed," for
|
||||
# example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
|
||||
# respective *-inverted property property results in a
|
||||
# respective *-inverted property results in a
|
||||
# double-inversion and actually means the "normal" line polarity is
|
||||
# in effect.
|
||||
wp-inverted:
|
||||
@@ -272,7 +272,7 @@ properties:
|
||||
mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
|
||||
waiting for I/O signalling and card power supply to be stable,
|
||||
regardless of whether pwrseq-simple is used. Default to 10ms if
|
||||
no available.
|
||||
not available.
|
||||
default: 10
|
||||
|
||||
supports-cqe:
|
||||
|
||||
@@ -149,7 +149,7 @@ properties:
|
||||
- description:
|
||||
The first register range should be the one of the DWMAC controller
|
||||
- description:
|
||||
The second range is is for the Amlogic specific configuration
|
||||
The second range is for the Amlogic specific configuration
|
||||
(for example the PRG_ETHERNET register range on Meson8b and newer)
|
||||
|
||||
interrupts:
|
||||
|
||||
@@ -222,7 +222,7 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
This define the LED index in the PHY or the MAC. It's really
|
||||
This defines the LED index in the PHY or the MAC. It's really
|
||||
driver dependent and required for ports that define multiple
|
||||
LED for the same port.
|
||||
|
||||
|
||||
@@ -266,7 +266,7 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
This define the LED index in the PHY or the MAC. It's really
|
||||
This defines the LED index in the PHY or the MAC. It's really
|
||||
driver dependent and required for ports that define multiple
|
||||
LED for the same port.
|
||||
|
||||
|
||||
@@ -13,7 +13,7 @@ KSZ9021:
|
||||
|
||||
All skew control options are specified in picoseconds. The minimum
|
||||
value is 0, the maximum value is 3000, and it can be specified in 200ps
|
||||
steps, *but* these values are in not fact what you get because this chip's
|
||||
steps, *but* these values are in no way what you get because this chip's
|
||||
skew values actually increase in 120ps steps, starting from -840ps. The
|
||||
incorrect values came from an error in the original KSZ9021 datasheet
|
||||
before it was corrected in revision 1.2 (Feb 2014), but it is too late to
|
||||
@@ -153,7 +153,7 @@ KSZ9031:
|
||||
- micrel,force-master:
|
||||
Boolean, force phy to master mode. Only set this option if the phy
|
||||
reference clock provided at CLK125_NDO pin is used as MAC reference
|
||||
clock because the clock jitter in slave mode is to high (errata#2).
|
||||
clock because the clock jitter in slave mode is too high (errata#2).
|
||||
Attention: The link partner must be configurable as slave otherwise
|
||||
no link will be established.
|
||||
|
||||
|
||||
@@ -26,7 +26,7 @@ Optional properties:
|
||||
Setting the RMII Reference Clock Select bit enables 25 MHz rather
|
||||
than 50 MHz clock mode.
|
||||
|
||||
Note that this option in only needed for certain PHY revisions with a
|
||||
Note that this option is only needed for certain PHY revisions with a
|
||||
non-standard, inverted function of this configuration bit.
|
||||
Specifically, a clock reference ("rmii-ref" below) is always needed to
|
||||
actually select a mode.
|
||||
|
||||
@@ -108,6 +108,7 @@ examples:
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
gic: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
@@ -42,6 +42,9 @@ properties:
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
@@ -92,6 +95,7 @@ examples:
|
||||
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
@@ -101,6 +101,9 @@ patternProperties:
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
|
||||
@@ -56,6 +56,9 @@ properties:
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
@@ -109,6 +112,7 @@ examples:
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
@@ -99,6 +99,9 @@ properties:
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
|
||||
142
Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
Normal file
142
Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
Normal file
@@ -0,0 +1,142 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/perf/apm,xgene-pmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene SoC PMU
|
||||
|
||||
maintainers:
|
||||
- Khuong Dinh <khuong@os.amperecomputing.com>
|
||||
|
||||
description: |
|
||||
This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
|
||||
The following PMU devices are supported:
|
||||
|
||||
L3C - L3 cache controller
|
||||
IOB - IO bridge
|
||||
MCB - Memory controller bridge
|
||||
MC - Memory controller
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- apm,xgene-pmu
|
||||
- apm,xgene-pmu-v2
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 2
|
||||
|
||||
ranges: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
regmap-csw:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
regmap-mcba:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
regmap-mcbb:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- regmap-csw
|
||||
- regmap-mcba
|
||||
- regmap-mcbb
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- apm,xgene-pmu-l3c
|
||||
- apm,xgene-pmu-iob
|
||||
- apm,xgene-pmu-mcb
|
||||
- apm,xgene-pmu-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
enable-bit-index:
|
||||
description:
|
||||
Specifies which bit enables the associated resource in MCB or MC subnodes.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 31
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pmu@78810000 {
|
||||
compatible = "apm,xgene-pmu-v2";
|
||||
reg = <0x0 0x78810000 0x0 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
regmap-csw = <&csw>;
|
||||
regmap-mcba = <&mcba>;
|
||||
regmap-mcbb = <&mcbb>;
|
||||
interrupts = <0x0 0x22 0x4>;
|
||||
|
||||
pmul3c@7e610000 {
|
||||
compatible = "apm,xgene-pmu-l3c";
|
||||
reg = <0x0 0x7e610000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pmuiob@7e940000 {
|
||||
compatible = "apm,xgene-pmu-iob";
|
||||
reg = <0x0 0x7e940000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pmucmcb@7e710000 {
|
||||
compatible = "apm,xgene-pmu-mcb";
|
||||
reg = <0x0 0x7e710000 0x0 0x1000>;
|
||||
enable-bit-index = <0>;
|
||||
};
|
||||
|
||||
pmucmcb@7e730000 {
|
||||
compatible = "apm,xgene-pmu-mcb";
|
||||
reg = <0x0 0x7e730000 0x0 0x1000>;
|
||||
enable-bit-index = <1>;
|
||||
};
|
||||
|
||||
pmucmc@7e810000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e810000 0x0 0x1000>;
|
||||
enable-bit-index = <0>;
|
||||
};
|
||||
|
||||
pmucmc@7e850000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e850000 0x0 0x1000>;
|
||||
enable-bit-index = <1>;
|
||||
};
|
||||
|
||||
pmucmc@7e890000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e890000 0x0 0x1000>;
|
||||
enable-bit-index = <2>;
|
||||
};
|
||||
|
||||
pmucmc@7e8d0000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e8d0000 0x0 0x1000>;
|
||||
enable-bit-index = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,112 +0,0 @@
|
||||
* APM X-Gene SoC PMU bindings
|
||||
|
||||
This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
|
||||
The following PMU devices are supported:
|
||||
|
||||
L3C - L3 cache controller
|
||||
IOB - IO bridge
|
||||
MCB - Memory controller bridge
|
||||
MC - Memory controller
|
||||
|
||||
The following section describes the SoC PMU DT node binding.
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall be "apm,xgene-pmu" for revision 1 or
|
||||
"apm,xgene-pmu-v2" for revision 2.
|
||||
- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
|
||||
- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
|
||||
- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
|
||||
- reg : First resource shall be the CPU bus PMU resource.
|
||||
- interrupts : Interrupt-specifier for PMU IRQ.
|
||||
|
||||
Required properties for L3C subnode:
|
||||
- compatible : Shall be "apm,xgene-pmu-l3c".
|
||||
- reg : First resource shall be the L3C PMU resource.
|
||||
|
||||
Required properties for IOB subnode:
|
||||
- compatible : Shall be "apm,xgene-pmu-iob".
|
||||
- reg : First resource shall be the IOB PMU resource.
|
||||
|
||||
Required properties for MCB subnode:
|
||||
- compatible : Shall be "apm,xgene-pmu-mcb".
|
||||
- reg : First resource shall be the MCB PMU resource.
|
||||
- enable-bit-index : The bit indicates if the according MCB is enabled.
|
||||
|
||||
Required properties for MC subnode:
|
||||
- compatible : Shall be "apm,xgene-pmu-mc".
|
||||
- reg : First resource shall be the MC PMU resource.
|
||||
- enable-bit-index : The bit indicates if the according MC is enabled.
|
||||
|
||||
Example:
|
||||
csw: csw@7e200000 {
|
||||
compatible = "apm,xgene-csw", "syscon";
|
||||
reg = <0x0 0x7e200000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
mcba: mcba@7e700000 {
|
||||
compatible = "apm,xgene-mcb", "syscon";
|
||||
reg = <0x0 0x7e700000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
mcbb: mcbb@7e720000 {
|
||||
compatible = "apm,xgene-mcb", "syscon";
|
||||
reg = <0x0 0x7e720000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pmu: pmu@78810000 {
|
||||
compatible = "apm,xgene-pmu-v2";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
regmap-csw = <&csw>;
|
||||
regmap-mcba = <&mcba>;
|
||||
regmap-mcbb = <&mcbb>;
|
||||
reg = <0x0 0x78810000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x22 0x4>;
|
||||
|
||||
pmul3c@7e610000 {
|
||||
compatible = "apm,xgene-pmu-l3c";
|
||||
reg = <0x0 0x7e610000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pmuiob@7e940000 {
|
||||
compatible = "apm,xgene-pmu-iob";
|
||||
reg = <0x0 0x7e940000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pmucmcb@7e710000 {
|
||||
compatible = "apm,xgene-pmu-mcb";
|
||||
reg = <0x0 0x7e710000 0x0 0x1000>;
|
||||
enable-bit-index = <0>;
|
||||
};
|
||||
|
||||
pmucmcb@7e730000 {
|
||||
compatible = "apm,xgene-pmu-mcb";
|
||||
reg = <0x0 0x7e730000 0x0 0x1000>;
|
||||
enable-bit-index = <1>;
|
||||
};
|
||||
|
||||
pmucmc@7e810000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e810000 0x0 0x1000>;
|
||||
enable-bit-index = <0>;
|
||||
};
|
||||
|
||||
pmucmc@7e850000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e850000 0x0 0x1000>;
|
||||
enable-bit-index = <1>;
|
||||
};
|
||||
|
||||
pmucmc@7e890000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e890000 0x0 0x1000>;
|
||||
enable-bit-index = <2>;
|
||||
};
|
||||
|
||||
pmucmc@7e8d0000 {
|
||||
compatible = "apm,xgene-pmu-mc";
|
||||
reg = <0x0 0x7e8d0000 0x0 0x1000>;
|
||||
enable-bit-index = <3>;
|
||||
};
|
||||
};
|
||||
@@ -43,6 +43,8 @@ properties:
|
||||
the amount of cells must be specified as 2. See the below mentioned gpio
|
||||
binding representation for description of particular cells.
|
||||
|
||||
gpio-line-names: true
|
||||
|
||||
mediatek,pctl-regmap:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
|
||||
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Reference in New Issue
Block a user