Pull regulator updates from Mark Brown:
"The main updates for this release are around monitoring of regulators,
largely for error handling purposes. We allow the stream of regulator
events to be seen by userspace as netlink events and allow system
integrators to describe individual regulators as system critical with
information on how long the system is expected to last on error. The
system level error handling is very much about best effort problem
mitigation rather than providing something fully robust, the initial
drive was to provide a mechanism for trying to avoid initiating any
new writes to flash once we notice the power going out.
Otherwise it's very quiet, mainly several new Qualcomm devices.
- Support for marking regulators as system critical and providing
information on how long the system might last with those regulators
in a failure state, hooked into the existing critical shutdown
error handling.
- Optional support for generating netlink events for events, there
are use cases for system monitoring UIs and error handling.
- A command line option to leave unused controllable regulators
enabled, useful for debugging. We already only disable regulators
we were explicitly given permission to control.
- Support for Quacomm MP5496, PM8010 and PM8937"
* tag 'regulator-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: (31 commits)
regulator: event: Ensure atomicity for sequence number
uapi: regulator: Fix typo
regulator: Reuse LINEAR_RANGE() in REGULATOR_LINEAR_RANGE()
dt-bindings: regulator: qcom,usb-vbus-regulator: clean up example
regulator: qcom_smd: Add LDO5 MP5496 regulator
regulator: qcom-rpmh: add support for pm8010 regulators
regulator: dt-bindings: qcom,rpmh: add compatible for pm8010
regulator: qcom-rpmh: extend to support multiple linear voltage ranges
regulator: wm8350: Convert to platform remove callback returning void
regulator: virtual: Convert to platform remove callback returning void
regulator: userspace-consumer: Convert to platform remove callback returning void
regulator: uniphier: Convert to platform remove callback returning void
regulator: stm32-vrefbuf: Convert to platform remove callback returning void
regulator: db8500-prcmu: Convert to platform remove callback returning void
regulator: bd9571mwv: Convert to platform remove callback returning void
regulator: arizona-ldo1: Convert to platform remove callback returning void
regulator: event: Add regulator netlink event support
regulator: event: Add regulator netlink event support
regulator: stpmic1: Fix kernel-doc notation warnings
regulator: palmas: remove redundant initialization of pointer pdata
...
* clk-rs9:
clk: rs9: Add support for 9FGV0841
clk: rs9: Replace model check with bitshift from chip data
clk: rs9: Limit check to vendor ID in VID register
dt-bindings: clk: rs9: Add 9FGV0841
If the location of the kernel sources contains the string that we're
filtering for using DT_SCHEMA_FILES, then all schemas will currently be
matched, returned and checked, not just the ones we actually expected.
As an example, if the kernel sources happen to be below a directory
'google', and DT_SCHEMA_FILES=google, everything is checked. More
common examples might be having the sources below people's home
directories that contain the string st or arm and then searching for
those. The list is endless.
Fix this by only matching for schemas below the kernel source's
bindings directory.
Note that I opted for the implementation here so as to not having to
deal with escaping DT_SCHEMA_FILES, which would have been the
alternative if the grep match itself had been updated.
Cc: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20231220145537.2163811-1-andre.draszik@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the devicetree bindings for the Google Security Chip H1 running
Cr50 firmware to DT schema.
The chip can be attached to SPI or I²C. Existing devicetrees use the
same "google,cr50" compatible string for both cases without additionally
specifying a generic "tcg,tpm_tis-spi" or "tcg,tpm-tis-i2c" compatible.
The chip therefore cannot be documented in the tcg,tpm_tis-spi.yaml and
tcg,tpm-tis-i2c.yaml schemas: The validator would select both of them
and complain about SPI properties when the chip is an I²C peripheral.
So document the chip in a schema of its own which includes both, SPI and
I²C properties by reference.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/52635205818ab201cacb0c0f37c7fa48149c7f8e.1702806810.git.lukas@wunner.de
Signed-off-by: Rob Herring <robh@kernel.org>
A significant number of Trusted Platform Modules conform to the "TIS"
specification published by the Trusted Computing Group ("TCG PC Client
Specific TPM Interface Specification"). These chips typically use an
SPI, I²C or LPC bus as transport (via MMIO in the latter case). Some
of them even support multiple of those buses (selectable through a
config strap) or the same chip is available in multiple SKUs, each with
a different bus interface.
The devicetree bindings for these TPMs have not been converted to DT
schema yet and are spread out across 3 generic files and 2 chip-specific
files. A few TPM compatible strings were added to trivial-devices.yaml
even though additional properties are documented in the plaintext
bindings.
Consolidate the devicetree bindings into 3 yaml files, one per bus.
Move common properties to a separate tpm-common.yaml.
Document compatible strings which are supported by the TPM TIS driver
but were neglected to be added to the devicetree bindings.
Document the memory-region property recently introduced by commit
1e2714bb83 ("tpm: Add reserved memory event log").
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/953fd4c7519030db88e5b5e12ab6307414ebdd21.1702806810.git.lukas@wunner.de
Signed-off-by: Rob Herring <robh@kernel.org>
The iommus and iommu-names property schemas have several issues. First,
'iommus-names' in the if/then schemas is the wrong name. As all the names
are the same, they can be defined at the top level instead. Then the
if/then schemas just need to define how many entries. The iommus if/then
schemas are also redundant. Best I can tell, the desire was to require 2
entries for "samsung,exynos5433-mfc", "samsung,mfc-v5", "samsung,mfc-v6",
and "samsung,mfc-v8".
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Aakarsh Jain <aakarsh.jain@samsung.com>
Link: https://lore.kernel.org/r/20231214195553.862920-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Pull irq subsystem updates from Ingo Molnar:
- Add support for the IA55 interrupt controller on RZ/G3S SoC's
- Update/fix the Qualcom MPM Interrupt Controller driver's register
enumeration within the somewhat exotic "RPM Message RAM" MMIO-mapped
shared memory region that is used for other purposes as well
- Clean up the Xtensa built-in Programmable Interrupt Controller driver
(xtensa-pic) a bit
* tag 'irq-core-2024-01-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/irq-xtensa-pic: Clean up
irqchip/qcom-mpm: Support passing a slice of SRAM as reg space
dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
irqchip/renesas-rzg2l: Add support for suspend to RAM
irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
irqchip/renesas-rzg2l: Document structure members
irqchip/renesas-rzg2l: Align struct member names to tabs
irqchip/renesas-rzg2l: Use tabs instead of spaces
The correct property name is 'reg' not 'regs'.
Fixes: 68e89bb36d ("dt-bindings: display: samsung,exynos-mixer: convert to dtschema")
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Pull arm64 updates from Will Deacon:
"CPU features:
- Remove ARM64_HAS_NO_HW_PREFETCH copy_page() optimisation for ye
olde Thunder-X machines
- Avoid mapping KPTI trampoline when it is not required
- Make CPU capability API more robust during early initialisation
Early idreg overrides:
- Remove dependencies on core kernel helpers from the early
command-line parsing logic in preparation for moving this code
before the kernel is mapped
FPsimd:
- Restore kernel-mode fpsimd context lazily, allowing us to run
fpsimd code sequences in the kernel with pre-emption enabled
KBuild:
- Install 'vmlinuz.efi' when CONFIG_EFI_ZBOOT=y
- Makefile cleanups
LPA2 prep:
- Preparatory work for enabling the 'LPA2' extension, which will
introduce 52-bit virtual and physical addressing even with 4KiB
pages (including for KVM guests).
Misc:
- Remove dead code and fix a typo
MM:
- Pass NUMA node information for IRQ stack allocations
Perf:
- Add perf support for the Synopsys DesignWare PCIe PMU
- Add support for event counting thresholds (FEAT_PMUv3_TH)
introduced in Armv8.8
- Add support for i.MX8DXL SoCs to the IMX DDR PMU driver.
- Minor PMU driver fixes and optimisations
RIP VPIPT:
- Remove what support we had for the obsolete VPIPT I-cache policy
Selftests:
- Improvements to the SVE and SME selftests
Stacktrace:
- Refactor kernel unwind logic so that it can used by BPF unwinding
and, eventually, reliable backtracing
Sysregs:
- Update a bunch of register definitions based on the latest XML drop
from Arm"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (87 commits)
kselftest/arm64: Don't probe the current VL for unsupported vector types
efi/libstub: zboot: do not use $(shell ...) in cmd_copy_and_pad
arm64: properly install vmlinuz.efi
arm64/sysreg: Add missing system instruction definitions for FGT
arm64/sysreg: Add missing system register definitions for FGT
arm64/sysreg: Add missing ExtTrcBuff field definition to ID_AA64DFR0_EL1
arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1
arm64: memory: remove duplicated include
arm: perf: Fix ARCH=arm build with GCC
arm64: Align boot cpucap handling with system cpucap handling
arm64: Cleanup system cpucap handling
MAINTAINERS: add maintainers for DesignWare PCIe PMU driver
drivers/perf: add DesignWare PCIe PMU driver
PCI: Move pci_clear_and_set_dword() helper to PCI header
PCI: Add Alibaba Vendor ID to linux/pci_ids.h
docs: perf: Add description for Synopsys DesignWare PCIe PMU driver
arm64: irq: set the correct node for shadow call stack
Revert "perf/arm_dmc620: Remove duplicate format attribute #defines"
arm64: fpsimd: Implement lazy restore for kernel mode FPSIMD
arm64: fpsimd: Preserve/restore kernel mode NEON at context switch
...
Revert "net: stmmac: Use interrupt mode INTM=1 for per channel irq"
This reverts commit 36af9f25dd.
Revert "net: stmmac: Add support for TX/RX channel interrupt"
This reverts commit 9072e03d32.
Revert "net: stmmac: Make MSI interrupt routine generic"
This reverts commit 477bd4beb9.
Revert "dt-bindings: net: snps,dwmac: per channel irq"
This reverts commit 67d47c8ada.
Device tree bindings need to be reviewed.
Link: https://lore.kernel.org/all/2df9fe3e-7971-4aa2-89a9-0e085b3b00d7@linaro.org/
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Move tas2563 from tas2562.yaml to tas2781.yaml to unbind tas2563 from
tas2562 driver code and bind it to tas2781 driver code, because tas2563
only work in bypass-DSP mode with tas2562 driver. In order to enable DSP
mode for tas2563, it has been moved to tas2781 driver. As to the hardware
part, such as register setting and DSP firmware, all these are stored in
the binary firmware. What tas2781 drivder does is to parse the firmware
and download it to the chip, then power on the chip. So, tas2781 driver
can be resued as tas2563 driver. Only attention will be paid to
downloading corresponding firmware.
Signed-off-by: Shenghao Ding <shenghao-ding@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://msgid.link/r/20240104145721.1398-1-shenghao-ding@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The high speed related interrupts present on QC targets are as follows:
1. dp/dm irq's
These IRQ's directly reflect changes on the DP/DM pads of the SoC. These
are used as wakeup interrupts only on SoCs with non-QUSB2 targets with
exception of SDM670/SDM845/SM6350.
2. qusb2_phy irq
SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a
single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL
register. The required DPSE/DMSE configuration is done in
QUSB2PHY_INTR_CTRL register of phy address space.
3. hs_phy_irq
This is completely different from the above two and is present on all
targets with exception of a few IPQ ones. The interrupt is not enabled by
default and its functionality is mutually exclusive of qusb2_phy on QUSB
targets and DP/DM on femto phy targets.
The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq"
when they should have been "qusb2_phy_irq". On Femto phy targets, the
"hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event",
neither of which would never be triggered directly are non-functional
currently. The implementation tries to clean up this issue by addressing
the discrepencies involved and fixing the hs_phy_irq's in respective DT's.
Classify SoC's into four groups based on whether qusb2_phy interrupt
or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the
SoCs have hs_phy_irq present in them or not. The ss_phy_irq is optional
interrupt because there are mutliple SoC's which either support only High
Speed or there are multiple controllers within same Soc and the secondary
controller is High Speed only capable.
This breaks ABI on targets running older kernels, but since the interrupt
definitions are given wrong on many targets and to establish proper rules
for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is
necessary. The bindings put pwr_event as the first interrupt and ss_phy as
the last. Since all SoCs have the pwr_event (HS) interrupt, but not all
controllers have the SS PHY interrupt, this would prevent, to some extent,
expressing that the SS PHY is optional by keeping it last in the binding
schema and making sure that minItems = maxItems - 1.
No new targets have been added to schema. Only the existing ones have been
re-ordered.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231227091951.685-2-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Commit 662a60102c ("usb: typec: Separate USB Power Delivery from USB
Type-C") allows userspace to configure the PD of a port by selecting
different set of predefined PD capabilities. Define the PD capability
sets in DT for better configurability in device modules.
Define an optional child node "capabilities" to contain multiple USB
Power Delivery capabilities.
Define child nodes with pattern (e.g. caps-0, caps-1) under
"capabilities". Each node contains PDO data of a selectable Power
Delivery capability.
Also define common properties for source-pdos, sink-pdos, and
op-sink-microwatt that can be referenced.
Signed-off-by: Kyle Tso <kyletso@google.com>
Link: https://lore.kernel.org/r/20231205030114.1349089-2-kyletso@google.com
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231216104630.2720818-2-kyletso@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The Ilitek ili2901 touch screen chip same as Elan eKTH6915 controller
has a reset gpio. The difference is that they have different
post_power_delay_ms and post_gpio_reset_on_delay_ms.
Ilitek ili2901 also uses 3.3V power supply.
Signed-off-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jiri Kosina <jkosina@suse.com>
One new boards, the CoolPi CM5 SoM and 4B SBC. Basic node for the rk3588
display controller and a bunch of small improvements for different boards,
* tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
arm64: dts: rockchip: Fix led pinctrl of lubancat 1
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
arm64: dts: rockchip: support poweroff on the rock-5b
arm64: dts: rockchip: Support poweroff on Orange Pi 5
arm64: dts: rockchip: nanopc-t6 sdmmc beautification
arm64: dts: rockchip: Fix rk3588 USB power-domain clocks
arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus lts
arm64: dts: rockchip: Support poweroff on NanoPC-T6
arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanup
arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB
dt-bindings: arm: rockchip: Add Cool Pi CM5
arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B
dt-bindings: arm: rockchip: Add Cool Pi 4B
dt-bindings: vendor-prefixes: Add Cool Pi
arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-e
arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikou
arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-puma
arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dts
arm64: dts: rockchip: Add vop on rk3588
...
Link: https://lore.kernel.org/r/3711719.VqM8IeB0Os@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM: sprd: DTS and bindings for v6.8-rc1
Unisoc ARM64 DTS and bindings changes are:
- Fixed a few dtb_check warnings
- Add bindings for a new SoC - UMS9620
- Fixed an issue on UMS512
* tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux:
arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings
arm64: dts: sprd: Add clock reference for pll2 on UMS512
arm64: dts: sprd: Removed unused clock references from etm nodes
arm64: dts: sprd: Add support for Unisoc's UMS9620
dt-bindings: arm: Add compatible strings for Unisoc's UMS9620
arm64: dts: sprd: fix the cpu node for UMS512
Link: https://lore.kernel.org/r/20231228084958.1439115-1-chunyan.zhang@unisoc.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
