Merge tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann: "A number of SoC platforms are adding modernized variants of their already supported chips time, with a total of 12 new SoCs, and two older SoC getting removed: - Qualcomm Glymur is a compute SoC using 18 Oryon-2 CPU cores - Qualcomm Mahua is a variant of Glymur with only 12 CPU cores, but largely identical. - Qualcomm Eliza is an embeded platform for mobile phone (SM7750) and IOT (QC7790S/M) workloads - Qualcomm IPQ5210 is a wireless networking SoC using Cortex-A53 cores - Qualcomm apq8084 and ipq806x had only rudimentary support but no actual products using them, so they are now gone. - Axis ARTPEC-9 is a follow-up to the ARTPEC-8 embedded SoC, using the Samsung SoC platform but now with Cortex-A55 cores - ARM Zena is a virtual platform in FVP using Cortex-A720AE cores, with additional versions planned to be merged in the future. - ARM corstone-1000-a320 is a reference platform for IOT, using low-end Cortex-A320 cores - Microchip LAN9691 is an updated 64-bit variant of the arm32 lan966x series of networking SoCs - Microchip PIC64GX is an embedded RISC-V chip using SIFIVE U54 CPU cores - Rockchip RV1103B is the low-end 32-bit single-core vision processor - Renesas RZ/G3L (r9a08g046) is an industrial embedded chip using Cortex-A55 cores, similar to the G3E and G3S variants we already supported. - NXP S32N79 is an automotive SoC using Cortex-A78AE cores, a significant upgrade from the older S32V and S32G series These all come with at least one reference board or an initial product using these, in total there are 67 newly added boards. The ones for already supported SoCs are: - Two more Aspeed BMC based boards - Three older tablets based on 32-bit OMAP4 and Exynos5 SoCs - One Set-top-box based on Allwinner H6 - 22 additional industrial/embedded boards using 64-bit NXP i.MX8M or i.MX9 SoCs - 20 Qualcomm SoC based machines across all possible markets: workstation, gaming, laptop, phone, networking, reference, ... - Three more Rockchips rk35xx based boards - Four variants of the Toradex Verdin using TI AM62 Other notable bits are: - A cleanup for the 32-bit Tegra paz00 board moved the last board specific code on Tegra into equivalent dts syntax. - There continues to be a significant number of fixes for static checking of dtc syntax, but it feels like this is slowing down, hopefully getting into a state where most known issues are addressed - Additional hardware support for many existing boards across SoC families, notably Qualcomm, Broadcom, i.MX2, i.MX6, Rockchips, STM32, Mediatek, Tegra, TI and Microchip" * tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (841 commits) arm64: dts: ti: k3: Use memory-region-names for r5f ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif ARM: dts: imx25: rename node name tcq to touchscreen ARM: dts: imx: b850v3: Disable unused usdhc4 ARM: dts: imx: b850v3: Define GPIO line names ARM: dts: imx: b850v3: Use alphabetical sorting ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps ARM: dts: imx7ulp: Add CPU clock and OPP table support ARM: dts: imx7-mba7: Deassert BOOT_EN after boot ARM: dts: tqma7: add boot phase properties ARM: dts: imx7s: add boot phase properties ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems ARM: dts: mba6ulx: add boot phase properties ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties ARM: dts: imx6ul/imx6ull: add boot phase properties ARM: dts: imx6qdl-mba6: add boot phase properties ARM: dts: imx6qdl-tqma6: add boot phase properties ARM: dts: imx6qdl: add boot phase properties ...
2026-04-18 06:44:00 -04:00 · 2026-04-16 20:28:48 -07:00
parent 440d6635b2 41d7004ab4
commit e65f4718a5
806 changed files with 80915 additions and 11630 deletions
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -84,6 +84,12 @@ properties:
              - altr,socfpga-stratix10-swvp
          - const: altr,socfpga-stratix10

+      - description: Stratix 10 SoCDK eMMC variant
+        items:
+          - const: altr,socfpga-stratix10-socdk-emmc
+          - const: altr,socfpga-stratix10-socdk
+          - const: altr,socfpga-stratix10
+
      - description: AgileX boards
        items:
          - enum:
@@ -105,6 +111,7 @@ properties:
          - enum:
              - intel,socfpga-agilex5-socdk
              - intel,socfpga-agilex5-socdk-013b
+              - intel,socfpga-agilex5-socdk-modular
              - intel,socfpga-agilex5-socdk-nand
          - const: intel,socfpga-agilex5

--- a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
@@ -15,11 +15,11 @@ description: |+
  provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
  processors.

-  Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
-  systems for M-Class (or other) processors for adding sensors, connectivity,
-  video, audio and machine learning at the edge System and security IPs to build
-  a secure SoC for a range of rich IoT applications, for example gateways, smart
-  cameras and embedded systems.
+  Support for Cortex‑A32, Cortex‑A35, Cortex‑A53 and Cortex-A320 processors.
+  Two expansion systems for M-Class (or other) processors for adding sensors,
+  connectivity, video, audio and machine learning at the edge System and
+  security IPs to build a secure SoC for a range of rich IoT applications, for
+  example gateways, smart cameras and embedded systems.

  Integrated Secure Enclave providing hardware Root of Trust and supporting
  seamless integration of the optional CryptoCell™-312 cryptographic
@@ -39,6 +39,11 @@ properties:
          implementation of this system. See ARM ecosystems FVP's.
        items:
          - const: arm,corstone1000-fvp
+      - description: Corstone1000-A320 FVP is the Fixed Virtual Platform
+          implementation of this system with Cortex-A320 cores and Ethos-U85
+          NPU. See ARM ecosystems FVP's.
+        items:
+          - const: arm,corstone1000-a320-fvp

 additionalProperties: true

--- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
@@ -119,6 +119,16 @@ properties:
        items:
          - const: arm,foundation-aarch64
          - const: arm,vexpress
+      - description: Arm Zena Compute Subsystem Platforms
+          Arm Zena Compute Subsystem (CSS) is a compute platform targeting
+          the automotive sector. Arm Zena CSS is a high-performance Arm
+          Cortex-A720AE Application Processor system augmented with an Arm
+          Cortex-R82AE based Safety Island and real-time domain.
+        items:
+          - enum:
+              - arm,zena-css-fvp
+          - const: arm,zena-css
+          - const: arm,vexpress

  arm,vexpress,position:
    description: When daughterboards are stacked on one site, their position
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -35,6 +35,7 @@ properties:
              - ampere,mtjade-bmc
              - aspeed,ast2500-evb
              - asrock,altrad8-bmc
+              - asrock,ast2500-paul-ipmi-card
              - asrock,e3c246d4i-bmc
              - asrock,e3c256d4i-bmc
              - asrock,romed8hm3-bmc
@@ -80,6 +81,7 @@ properties:
              - ampere,mtmitchell-bmc
              - aspeed,ast2600-evb
              - aspeed,ast2600-evb-a1
+              - asus,ast2600-kommando-ipmi-card
              - asus,x4tf-bmc
              - facebook,anacapa-bmc
              - facebook,bletchley-bmc
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -243,6 +243,12 @@ properties:
          - const: microchip,lan9668
          - const: microchip,lan966

+      - description: Microchip LAN9696 EV23X71A Evaluation Board
+        items:
+          - const: microchip,ev23x71a
+          - const: microchip,lan9696
+          - const: microchip,lan9691
+
      - description: Kontron KSwitch D10 MMT series
        items:
          - enum:
--- a/Documentation/devicetree/bindings/arm/axis.yaml
+++ b/Documentation/devicetree/bindings/arm/axis.yaml
@@ -31,6 +31,12 @@ properties:
              - axis,artpec8-grizzly
          - const: axis,artpec8

+      - description: Axis ARTPEC-9 SoC board
+        items:
+          - enum:
+              - axis,artpec9-alfred
+          - const: axis,artpec9
+
 additionalProperties: true

 ...
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -218,6 +218,13 @@ properties:
      - qcom,kryo685
      - qcom,kryo780
      - qcom,oryon
+      - qcom,oryon-1-1
+      - qcom,oryon-1-2
+      - qcom,oryon-1-3
+      - qcom,oryon-1-4
+      - qcom,oryon-2-1
+      - qcom,oryon-2-2
+      - qcom,oryon-2-3
      - qcom,scorpion
      - samsung,mongoose-m2
      - samsung,mongoose-m3
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
@@ -49,38 +49,37 @@ required:
  - '#clock-cells'

 allOf:
- - if:
-     properties:
-       compatible:
-         contains:
-           enum:
-             - mediatek,mt2701-audsys
-             - mediatek,mt7622-audsys
-   then:
-     properties:
-       audio-controller:
-         $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mediatek,mt2701-audsys
+              - mediatek,mt7622-audsys
+    then:
+      properties:
+        audio-controller:
+          $ref: /schemas/sound/mediatek,mt2701-audio.yaml#

- - if:
-     properties:
-       compatible:
-         contains:
-           const: mediatek,mt8183-audiosys
-   then:
-     properties:
-       audio-controller:
-         $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
-
- - if:
-     properties:
-       compatible:
-         contains:
-           const: mediatek,mt8192-audsys
-   then:
-     properties:
-       audio-controller:
-         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt8183-audiosys
+    then:
+      properties:
+        audio-controller:
+          $ref: /schemas/sound/mediatek,mt8183-audio.yaml#

+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt8192-audsys
+    then:
+      properties:
+        audio-controller:
+          $ref: /schemas/sound/mt8192-afe-pcm.yaml#

 additionalProperties: false

--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -61,6 +61,21 @@ properties:
              - qcom,apq8084-sbc
          - const: qcom,apq8084

+      - items:
+          - enum:
+              - qcom,eliza-mtp
+          - const: qcom,eliza
+
+      - items:
+          - enum:
+              - qcom,glymur-crd
+          - const: qcom,glymur
+
+      - items:
+          - enum:
+              - qcom,mahua-crd
+          - const: qcom,mahua
+
      - items:
          - enum:
              - fairphone,fp6
@@ -171,6 +186,7 @@ properties:
              - qcom,msm8916-mtp
              - samsung,a3u-eur
              - samsung,a5u-eur
+              - samsung,coreprimeltevzw
              - samsung,e5
              - samsung,e7
              - samsung,fortuna3g
@@ -186,6 +202,7 @@ properties:
              - samsung,serranove
              - thwc,uf896
              - thwc,ufi001c
+              - wiko,chuppito
              - wingtech,wt86518
              - wingtech,wt86528
              - wingtech,wt88047
@@ -195,6 +212,8 @@ properties:
      - items:
          - enum:
              - xiaomi,riva
+              - xiaomi,rolex
+              - xiaomi,tiare
          - const: qcom,msm8917

      - items:
@@ -243,6 +262,13 @@ properties:
          - const: qcom,apq8096-sbc
          - const: qcom,apq8096

+      - items:
+          - const: arrow,apq8096sg-db820c
+          - const: arrow,apq8096-db820c
+          - const: qcom,apq8096-sbc
+          - const: qcom,apq8096sg
+          - const: qcom,apq8096
+
      - items:
          - enum:
              - oneplus,oneplus3
@@ -297,6 +323,11 @@ properties:
              - tplink,archer-ax55-v1
          - const: qcom,ipq5018

+      - items:
+          - enum:
+              - qcom,ipq5210-rdp504
+          - const: qcom,ipq5210
+
      - items:
          - enum:
              - qcom,ipq5332-ap-mi01.2
@@ -326,8 +357,10 @@ properties:
      - items:
          - enum:
              - qcom,ipq9574-ap-al02-c2
+              - qcom,ipq9574-ap-al02-c2-emmc
              - qcom,ipq9574-ap-al02-c6
              - qcom,ipq9574-ap-al02-c7
+              - qcom,ipq9574-ap-al02-c7-emmc
              - qcom,ipq9574-ap-al02-c8
              - qcom,ipq9574-ap-al02-c9
          - const: qcom,ipq9574
@@ -360,6 +393,7 @@ properties:
              - qcom,qcs6490-rb3gen2
              - radxa,dragon-q6a
              - shift,otter
+              - thundercomm,minipc-g1iot
              - thundercomm,rubikpi3
          - const: qcom,qcm6490

@@ -385,6 +419,7 @@ properties:
      - items:
          - enum:
              - acer,aspire1
+              - ecs,liva-qc710
              - qcom,sc7180-idp
          - const: qcom,sc7180

@@ -882,6 +917,7 @@ properties:

      - items:
          - enum:
+              - arduino,monza
              - qcom,monaco-evk
              - qcom,qcs8300-ride
          - const: qcom,qcs8300
@@ -889,6 +925,7 @@ properties:
      - items:
          - enum:
              - qcom,qcs615-ride
+              - qcom,talos-evk
          - const: qcom,qcs615
          - const: qcom,sm6150

@@ -972,6 +1009,7 @@ properties:
              - sony,pdx201
              - xiaomi,ginkgo
              - xiaomi,laurel-sprout
+              - xiaomi,willow
          - const: qcom,sm6125

      - items:
@@ -1063,6 +1101,7 @@ properties:

      - items:
          - enum:
+              - ayaneo,pocket-s2
              - qcom,sm8650-hdk
              - qcom,sm8650-mtp
              - qcom,sm8650-qrd
@@ -1110,6 +1149,7 @@ properties:
              - dell,xps13-9345
              - hp,elitebook-ultra-g1q
              - hp,omnibook-x14
+              - lenovo,ideacentre-mini-01q8x10
              - lenovo,yoga-slim7x
              - microsoft,romulus13
              - microsoft,romulus15
@@ -1128,6 +1168,12 @@ properties:
          - const: microsoft,denali
          - const: qcom,x1e80100

+      - items:
+          - enum:
+              - qcom,purwa-iot-evk
+          - const: qcom,purwa-iot-som
+          - const: qcom,x1p42100
+
      - items:
          - enum:
              - asus,zenbook-a14-ux3407qa-lcd
@@ -1137,6 +1183,7 @@ properties:

      - items:
          - enum:
+              - asus,vivobook-s15-x1p4
              - hp,omnibook-x14-fe1
              - lenovo,thinkbook-16
              - qcom,x1p42100-crd
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -754,6 +754,11 @@ properties:
          - const: khadas,edge2
          - const: rockchip,rk3588s

+      - description: Khadas Edge-2L series boards
+        items:
+          - const: khadas,edge-2l
+          - const: rockchip,rk3576
+
      - description: Kobol Helios64
        items:
          - const: kobol,helios64
@@ -808,11 +813,22 @@ properties:
          - const: netxeon,r89
          - const: rockchip,rk3288

+      - description: Onion Omega4 Evaluation board
+        items:
+          - const: onion,omega4-evb
+          - const: onion,omega4
+          - const: rockchip,rv1103b
+
      - description: OPEN AI LAB EAIDK-610
        items:
          - const: openailab,eaidk-610
          - const: rockchip,rk3399

+      - description: OneThing Edge Cube series
+        items:
+          - const: onething,edge-cube
+          - const: rockchip,rk3566
+
      - description: Xunlong Orange Pi RK3399 board
        items:
          - const: xunlong,rk3399-orangepi
@@ -1187,7 +1203,9 @@ properties:

      - description: Rockchip RK3576 Evaluation board
        items:
-          - const: rockchip,rk3576-evb1-v10
+          - enum:
+              - rockchip,rk3576-evb1-v10
+              - rockchip,rk3576-evb2-v10
          - const: rockchip,rk3576

      - description: Rockchip RK3588 Evaluation board
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -117,6 +117,7 @@ properties:
      - description: Exynos5250 based boards
        items:
          - enum:
+              - google,manta                    # Google Manta (Nexus 10)
              - google,snow-rev5                # Google Snow Rev 5+
              - google,spring                   # Google Spring
              - insignal,arndale                # Insignal Arndale
@@ -216,7 +217,9 @@ properties:
        items:
          - enum:
              - samsung,a2corelte               # Samsung Galaxy A2 Core
+              - samsung,j5y17lte                # Samsung Galaxy J5 (2017)
              - samsung,j6lte                   # Samsung Galaxy J6
+              - samsung,j7xelte                 # Samsung Galaxy J7 (2016)
              - samsung,on7xelte                # Samsung Galaxy J7 Prime
          - const: samsung,exynos7870

--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -183,10 +183,12 @@ properties:
          - const: seeed,stm32mp157c-odyssey-som
          - const: st,stm32mp157

-      - description: Phytec STM32MP1 SoM based Boards
+      - description: Phytec STM32MP157 SoM based Boards
        items:
-          - const: phytec,phycore-stm32mp1-3
-          - const: phytec,phycore-stm32mp157c-som
+          - enum:
+              - phytec,phycore-stm32mp1-3 # phyBOARD-Sargas with phyCORE-STM32MP157C SoM
+          - enum:
+              - phytec,phycore-stm32mp157c-som # phyCORE-STM32MP157C SoM
          - const: st,stm32mp157

      - description: Ultratronik STM32MP1 SBC based Boards
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -901,6 +901,11 @@ properties:
          - const: allwinner,sl631
          - const: allwinner,sun8i-v3

+      - description: TaiqiCat A01
+        items:
+          - const: ultrapower,taiqicat-a01
+          - const: allwinner,sun50i-h6
+
      - description: Tanix TX1
        items:
          - const: oranth,tanix-tx1
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -79,6 +79,7 @@ properties:
              - toradex,verdin-am62-nonwifi-ivy    # Verdin AM62 Module on Ivy
              - toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
              - toradex,verdin-am62-nonwifi-yavia  # Verdin AM62 Module on Yavia
+              - toradex,verdin-am62-nonwifi-zinnia # Verdin AM62 Module on Zinnia
          - const: toradex,verdin-am62-nonwifi     # Verdin AM62 Module without Wi-Fi / BT
          - const: toradex,verdin-am62             # Verdin AM62 Module
          - const: ti,am625
@@ -91,6 +92,7 @@ properties:
              - toradex,verdin-am62-wifi-ivy    # Verdin AM62 Wi-Fi / BT Module on Ivy
              - toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
              - toradex,verdin-am62-wifi-yavia  # Verdin AM62 Wi-Fi / BT Module on Yavia
+              - toradex,verdin-am62-wifi-zinnia # Verdin AM62 Wi-Fi / BT Module on Zinnia
          - const: toradex,verdin-am62-wifi     # Verdin AM62 Wi-Fi / BT Module
          - const: toradex,verdin-am62          # Verdin AM62 Module
          - const: ti,am625
@@ -103,6 +105,7 @@ properties:
              - toradex,verdin-am62p-nonwifi-ivy    # Verdin AM62P Module on Ivy
              - toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow
              - toradex,verdin-am62p-nonwifi-yavia  # Verdin AM62P Module on Yavia
+              - toradex,verdin-am62p-nonwifi-zinnia # Verdin AM62P Module on Zinnia
          - const: toradex,verdin-am62p-nonwifi     # Verdin AM62P Module without Wi-Fi / BT
          - const: toradex,verdin-am62p             # Verdin AM62P Module
          - const: ti,am62p5
@@ -115,6 +118,7 @@ properties:
              - toradex,verdin-am62p-wifi-ivy    # Verdin AM62P Wi-Fi / BT Module on Ivy
              - toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow
              - toradex,verdin-am62p-wifi-yavia  # Verdin AM62P Wi-Fi / BT Module on Yavia
+              - toradex,verdin-am62p-wifi-zinnia # Verdin AM62P Wi-Fi / BT Module on Zinnia
          - const: toradex,verdin-am62p-wifi     # Verdin AM62P Wi-Fi / BT Module
          - const: toradex,verdin-am62p          # Verdin AM62P Module
          - const: ti,am62p5
@@ -208,7 +212,6 @@ properties:
        items:
          - enum:
              - beagle,am67a-beagley-ai
-              - kontron,sa67             # Kontron SMARC-sAM67 board
              - ti,j722s-evm
          - const: ti,j722s

--- a/Documentation/devicetree/bindings/arm/ti/omap.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml
@@ -144,6 +144,8 @@ properties:
              - motorola,droid-bionic   # Motorola Droid Bionic XT875
              - motorola,xyboard-mz609
              - motorola,xyboard-mz617
+              - samsung,espresso7
+              - samsung,espresso10
              - ti,omap4-panda
              - ti,omap4-sdp
          - const: ti,omap4430
--- a/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml
@@ -0,0 +1,232 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC-9 SoC clock controller
+
+maintainers:
+  - Jesper Nilsson <jesper.nilsson@axis.com>
+
+description: |
+  ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)
+  units, generating clocks for different domains. Those CMU units are modeled
+  as separate device tree nodes, and might depend on each other.
+  The root clock in that root tree is an external clock: OSCCLK (25 MHz).
+  This external clock must be defined as a fixed-rate clock in dts.
+
+  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers, all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_CMU.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/axis,artpec9-clk.h' header.
+
+properties:
+  compatible:
+    enum:
+      - axis,artpec9-cmu-cmu
+      - axis,artpec9-cmu-bus
+      - axis,artpec9-cmu-core
+      - axis,artpec9-cmu-cpucl
+      - axis,artpec9-cmu-fsys0
+      - axis,artpec9-cmu-fsys1
+      - axis,artpec9-cmu-imem
+      - axis,artpec9-cmu-peri
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-cmu
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+
+        clock-names:
+          items:
+            - const: fin_pll
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-bus
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_BUS bus clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: bus
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_CORE main clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: main
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-cpucl
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_CPUCL switch clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: switch
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-fsys0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_FSYS0 bus clock (from CMU_CMU)
+            - description: CMU_FSYS0 IP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: bus
+            - const: ip
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-fsys1
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_FSYS1 scan0 clock (from CMU_CMU)
+            - description: CMU_FSYS1 scan1 clock (from CMU_CMU)
+            - description: CMU_FSYS1 bus clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: scan0
+            - const: scan1
+            - const: bus
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-imem
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_IMEM ACLK clock (from CMU_CMU)
+            - description: CMU_IMEM CA5 clock (from CMU_CMU)
+            - description: CMU_IMEM JPEG clock (from CMU_CMU)
+            - description: CMU_IMEM SSS clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: aclk
+            - const: ca5
+            - const: jpeg
+            - const: sss
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec9-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_PERI IP clock (from CMU_CMU)
+            - description: CMU_PERI DISP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: ip
+            - const: disp
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_FSYS1
+  - |
+    #include <dt-bindings/clock/axis,artpec9-clk.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cmu_fsys1: clock-controller@14c10000 {
+            compatible = "axis,artpec9-cmu-fsys1";
+            reg = <0x0 0x14c10000 0x0 0x4000>;
+            #clock-cells = <1>;
+            clocks = <&fin_pll>,
+                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
+                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
+                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
+            clock-names = "fin_pll", "scan0", "scan1", "bus";
+        };
+    };
+...
--- a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ5210
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on IPQ5210
+
+  See also:
+    include/dt-bindings/clock/qcom,ipq5210-gcc.h
+    include/dt-bindings/reset/qcom,ipq5210-gcc.h
+
+properties:
+  compatible:
+    const: qcom,ipq5210-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+      - description: PCIE30 PHY0 pipe clock source
+      - description: PCIE30 PHY1 pipe clock source
+      - description: USB3 PHY pipe clock source
+      - description: NSS common clock source
+
+  '#power-domain-cells': false
+
+  '#interconnect-cells':
+    const: 1
+
+required:
+  - compatible
+  - clocks
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    clock-controller@1800000 {
+      compatible = "qcom,ipq5210-gcc";
+      reg = <0x01800000 0x40000>;
+      clocks = <&xo_board_clk>,
+               <&sleep_clk>,
+               <&pcie30_phy0_pipe_clk>,
+               <&pcie30_phy1_pipe_clk>,
+               <&usb3phy_0_cc_pipe_clk>,
+               <&nss_cmn_clk>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
+...
--- a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
@@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Milos

 maintainers:
  - Luca Weiss <luca.weiss@fairphone.com>
+  - Taniya Das <taniya.das@oss.qualcomm.com>

 description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on Milos.

-  See also: include/dt-bindings/clock/qcom,milos-gcc.h
+  See also:
+   - include/dt-bindings/clock/qcom,eliza-gcc.h
+   - include/dt-bindings/clock/qcom,milos-gcc.h

 properties:
  compatible:
-    const: qcom,milos-gcc
+    enum:
+      - qcom,eliza-gcc
+      - qcom,milos-gcc

  clocks:
    items:
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -17,6 +17,7 @@ description: |
 properties:
  compatible:
    enum:
+      - qcom,eliza-rpmh-clk
      - qcom,glymur-rpmh-clk
      - qcom,kaanapali-rpmh-clk
      - qcom,milos-rpmh-clk
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -15,6 +15,7 @@ description: |
  power domains on SM8550

  See also:
+  - include/dt-bindings/clock/qcom,eliza-tcsr.h
  - include/dt-bindings/clock/qcom,glymur-tcsr.h
  - include/dt-bindings/clock/qcom,sm8550-tcsr.h
  - include/dt-bindings/clock/qcom,sm8650-tcsr.h
@@ -24,6 +25,7 @@ properties:
  compatible:
    items:
      - enum:
+          - qcom,eliza-tcsr
          - qcom,glymur-tcsr
          - qcom,kaanapali-tcsr
          - qcom,milos-tcsr
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -28,19 +28,30 @@ properties:
      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
      - renesas,r9a07g054-cpg # RZ/V2L
      - renesas,r9a08g045-cpg # RZ/G3S
+      - renesas,r9a08g046-cpg # RZ/G3L
      - renesas,r9a09g011-cpg # RZ/V2M

  reg:
    maxItems: 1

  clocks:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Clock source to CPG can be either from external clock
+                     input (EXCLK) or crystal oscillator (XIN/XOUT).
+      - description: ETH0 TXC clock input
+      - description: ETH0 RXC clock input
+      - description: ETH1 TXC clock input
+      - description: ETH1 RXC clock input

  clock-names:
-    description:
-      Clock source to CPG can be either from external clock input (EXCLK) or
-      crystal oscillator (XIN/XOUT).
-    const: extal
+    minItems: 1
+    items:
+      - const: extal
+      - const: eth0_txc_tx_clk
+      - const: eth0_rxc_rx_clk
+      - const: eth1_txc_tx_clk
+      - const: eth1_rxc_rx_clk

  '#clock-cells':
    description: |
@@ -74,6 +85,25 @@ required:
  - '#power-domain-cells'
  - '#reset-cells'

+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g046-cpg
+    then:
+      properties:
+        clocks:
+          minItems: 5
+        clock-names:
+          minItems: 5
+    else:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          maxItems: 1
+
 additionalProperties: false

 examples:
--- a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
@@ -17,6 +17,7 @@ description:
 properties:
  compatible:
    enum:
+      - rockchip,rv1103b-cru
      - rockchip,rv1126b-cru

  reg:
--- a/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml
+++ b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml
@@ -16,12 +16,7 @@ description: |

 properties:
  compatible:
-    oneOf:
-      - items:
-          - enum:
-              - kontron,sa67mcu
-          - const: kontron,sl28cpld
-      - const: kontron,sl28cpld
+    const: kontron,sl28cpld

  reg:
    description:
--- a/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC
+
+maintainers:
+  - Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
+
+description: |
+  RPMh interconnect providers support system bandwidth requirements through
+  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+  able to communicate with the BCM through the Resource State Coordinator (RSC)
+  associated with each execution environment. Provider nodes must point to at
+  least one RPMh device child node pertaining to their RSC and each provider
+  can map to multiple RPMh resources.
+
+  See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,eliza-aggre1-noc
+      - qcom,eliza-aggre2-noc
+      - qcom,eliza-clk-virt
+      - qcom,eliza-cnoc-cfg
+      - qcom,eliza-cnoc-main
+      - qcom,eliza-gem-noc
+      - qcom,eliza-lpass-ag-noc
+      - qcom,eliza-lpass-lpiaon-noc
+      - qcom,eliza-lpass-lpicx-noc
+      - qcom,eliza-mc-virt
+      - qcom,eliza-mmss-noc
+      - qcom,eliza-nsp-noc
+      - qcom,eliza-pcie-anoc
+      - qcom,eliza-system-noc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+required:
+  - compatible
+
+allOf:
+  - $ref: qcom,rpmh-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-clk-virt
+              - qcom,eliza-mc-virt
+    then:
+      properties:
+        reg: false
+    else:
+      required:
+        - reg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-aggre1-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre UFS PHY AXI clock
+            - description: aggre USB3 PRIM AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-aggre2-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: RPMH CC IPA clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-pcie-anoc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre-NOC PCIe AXI clock
+            - description: cfg-NOC PCIe a-NOC AHB clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-aggre1-noc
+              - qcom,eliza-aggre2-noc
+              - qcom,eliza-pcie-anoc
+    then:
+      required:
+        - clocks
+    else:
+      properties:
+        clocks: false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    gem_noc: interconnect@24100000 {
+        compatible = "qcom,eliza-gem-noc";
+        reg = <0x24100000 0x163080>;
+        #interconnect-cells = <2>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+    };
+
+    mc_virt: interconnect-2 {
+        compatible = "qcom,eliza-mc-virt";
+        #interconnect-cells = <2>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+    };
+
+    aggre1_noc: interconnect@16e0000 {
+        compatible = "qcom,eliza-aggre1-noc";
+        reg = <0x16e0000 0x16400>;
+        #interconnect-cells = <2>;
+        clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+    };
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -28,6 +28,7 @@ properties:
          - const: qcom,osm-l3
      - items:
          - enum:
+              - qcom,eliza-epss-l3
              - qcom,sa8775p-epss-l3
              - qcom,sc7280-epss-l3
              - qcom,sc8280xp-epss-l3
--- a/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
+++ b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
@@ -21,6 +21,7 @@ properties:
          - enum:
              - allwinner,sun20i-d1-ledc
              - allwinner,sun50i-r329-ledc
+              - allwinner,sun55i-a523-ledc
          - const: allwinner,sun50i-a100-ledc

  reg:
--- a/Documentation/devicetree/bindings/npu/arm,ethos.yaml
+++ b/Documentation/devicetree/bindings/npu/arm,ethos.yaml
@@ -30,7 +30,7 @@ properties:
              - fsl,imx93-npu
          - const: arm,ethos-u65
      - items:
-          - {}
+          - const: arm,corstone1000-ethos-u85
          - const: arm,ethos-u85

  reg:
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 PCIe controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-pcie
+
+  reg:
+    description: |
+      Of the six PCIe controllers found on Tegra264, one (C0) is used for the
+      internal GPU and the other five (C1-C5) are routed to connectors such as
+      PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
+      through C5, but not for C0.
+    minItems: 4
+    items:
+      - description: ECAM-compatible configuration space
+      - description: application layer registers
+      - description: transaction layer registers
+      - description: privileged transaction layer registers
+      - description: data link/physical layer registers (not available on C0)
+
+  reg-names:
+    minItems: 4
+    items:
+      - const: ecam
+      - const: xal
+      - const: xtl
+      - const: xtl-pri
+      - const: xpl
+
+  interrupts:
+    minItems: 1
+    maxItems: 4
+
+  dma-coherent: true
+
+  nvidia,bpmp:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+      Must contain a pair of phandle (to the BPMP controller node) and
+      controller ID. The following are the controller IDs for each controller:
+
+      0: C0
+      1: C1
+      2: C2
+      3: C3
+      4: C4
+      5: C5
+    items:
+      - items:
+          - description: phandle to the BPMP controller node
+          - description: PCIe controller ID
+            maximum: 5
+
+required:
+  - interrupt-map
+  - interrupt-map-mask
+  - iommu-map
+  - msi-map
+  - nvidia,bpmp
+
+allOf:
+  - $ref: /schemas/pci/pci-host-bridge.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pci@c000000 {
+        compatible = "nvidia,tegra264-pcie";
+        reg = <0xd0 0xb0000000 0x0 0x10000000>,
+              <0x00 0x0c000000 0x0 0x00004000>,
+              <0x00 0x0c004000 0x0 0x00001000>,
+              <0x00 0x0c005000 0x0 0x00001000>;
+        reg-names = "ecam", "xal", "xtl", "xtl-pri";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        linux,pci-domain = <0x00>;
+        #interrupt-cells = <0x1>;
+
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,
+                        <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,
+                        <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,
+                        <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;
+
+        iommu-map = <0x0 &smmu2 0x10000 0x10000>;
+        msi-map = <0x0 &its 0x210000 0x10000>;
+        dma-coherent;
+
+        ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,
+                 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,
+                 <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;
+        bus-range = <0x0 0xff>;
+
+        nvidia,bpmp = <&bpmp 0>;
+      };
+    };
+
+  - |
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pci@8400000 {
+        compatible = "nvidia,tegra264-pcie";
+        reg = <0xa8 0xb0000000 0x0 0x10000000>,
+              <0x00 0x08400000 0x0 0x00004000>,
+              <0x00 0x08404000 0x0 0x00001000>,
+              <0x00 0x08405000 0x0 0x00001000>,
+              <0x00 0x08410000 0x0 0x00010000>;
+        reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        linux,pci-domain = <0x01>;
+        #interrupt-cells = <1>;
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,
+                        <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,
+                        <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,
+                        <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;
+
+        iommu-map = <0x0 &smmu1 0x10000 0x10000>;
+        msi-map = <0x0 &its 0x110000 0x10000>;
+        dma-coherent;
+
+        ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,
+                 <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,
+                 <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;
+        bus-range = <0x00 0xff>;
+
+        nvidia,bpmp = <&bpmp 1>;
+      };
+    };
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -262,6 +262,23 @@ properties:
            ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
            ("Updated to ratified state.")

+        - const: supm
+          description: |
+            The standard Supm extension for pointer masking support in user
+            mode (U-mode) as ratified at commit d70011dde6c2 ("Update to
+            ratified state") of riscv-j-extension.
+
+            Supm represents a combination of underlying hardware capability
+            (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode
+            software configuration that enables pointer masking for U-mode.
+
+            DO NOT include this property in device trees targeting privileged
+            system software (S-mode or M-mode).
+
+            This property is only appropriate in device trees provided to
+            U-mode software where the next-higher-privilege-mode supports
+            Smnpm or Ssnpm and enables it for U-mode.
+
        - const: svade
          description: |
            The standard Svade supervisor-level extension for SW-managed PTE A/D
@@ -907,6 +924,16 @@ properties:
        then:
          contains:
            const: b
+      # Supm depends on Smnpm or Ssnpm
+      - if:
+          contains:
+            const: supm
+        then:
+          oneOf:
+            - contains:
+                const: smnpm
+            - contains:
+                const: ssnpm
      # Za64rs and Ziccrse depend on Zalrsc or A
      - if:
          contains:
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -4,14 +4,14 @@
 $id: http://devicetree.org/schemas/riscv/microchip.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#

-title: Microchip PolarFire SoC-based boards
+title: Microchip SoC-based boards

 maintainers:
  - Conor Dooley <conor.dooley@microchip.com>
  - Daire McNamara <daire.mcnamara@microchip.com>

 description:
-  Microchip PolarFire SoC-based boards
+  Microchip SoC-based boards

 properties:
  $nodename:
@@ -46,6 +46,9 @@ properties:
              - microchip,mpfs-sev-kit
              - sundance,polarberry
          - const: microchip,mpfs
+      - items:
+          - const: microchip,pic64gx-curiosity-kit
+          - const: microchip,pic64gx

 additionalProperties: true

--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -63,7 +63,9 @@ allOf:
      properties:
        compatible:
          contains:
-            const: spacemit,k1-uart
+            enum:
+              - spacemit,k1-uart
+              - spacemit,k3-uart
    then:
      properties:
        clock-names:
@@ -76,6 +78,7 @@ allOf:
          contains:
            enum:
              - spacemit,k1-uart
+              - spacemit,k3-uart
              - nxp,lpc1850-uart
    then:
      required:
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -63,6 +63,7 @@ properties:
              - rockchip,rk3588-vo0-grf
              - rockchip,rk3588-vo1-grf
              - rockchip,rk3588-vop-grf
+              - rockchip,rv1103b-ioc
              - rockchip,rv1108-usbgrf
          - const: syscon
      - items:
@@ -98,6 +99,7 @@ properties:
              - rockchip,rk3576-pmu0-grf
              - rockchip,rk3576-usb2phy-grf
              - rockchip,rk3588-usb2phy-grf
+              - rockchip,rv1103b-pmu-grf
              - rockchip,rv1108-grf
              - rockchip,rv1108-pmugrf
              - rockchip,rv1126-grf
@@ -231,6 +233,7 @@ allOf:
              - rockchip,rk3036-grf
              - rockchip,rk3308-grf
              - rockchip,rk3368-pmugrf
+              - rockchip,rv1103b-pmu-grf

    then:
      properties:
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -31,6 +31,7 @@ properties:
          - enum:
              - canaan,k210-clint       # Canaan Kendryte K210
              - eswin,eic7700-clint     # ESWIN EIC7700
+              - microchip,pic64gx-clint # Microchip PIC64GX
              - sifive,fu540-c000-clint # SiFive FU540
              - spacemit,k1-clint       # SpacemiT K1
              - spacemit,k3-clint       # SpacemiT K3
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -223,6 +223,8 @@ patternProperties:
    description: Axiado Corporation
  "^axis,.*":
    description: Axis Communications AB
+  "^ayaneo,.*":
+    description: Anyun Intelligent Technology (Hong Kong) Co., Ltd
  "^azoteq,.*":
    description: Azoteq (Pty) Ltd
  "^azw,.*":
@@ -1207,6 +1209,8 @@ patternProperties:
    description: One Laptop Per Child
  "^oneplus,.*":
    description: OnePlus Technology (Shenzhen) Co., Ltd.
+  "^onething,.*":
+    description: Shenzhen OneThing Technologies Co., Ltd.
  "^onie,.*":
    description: Open Network Install Environment group
  "^onion,.*":
@@ -1741,6 +1745,8 @@ patternProperties:
    description: Ufi Space Co., Ltd.
  "^ugoos,.*":
    description: Ugoos Industrial Co., Ltd.
+  "^ultrapower,.*":
+    description: Beijing Ultrapower Software Co., Ltd.
  "^uni-t,.*":
    description: Uni-Trend Technology (China) Co., Ltd.
  "^uniwest,.*":
@@ -1833,6 +1839,8 @@ patternProperties:
    description: Wi2Wi, Inc.
  "^widora,.*":
    description: Beijing Widora Technology Co., Ltd.
+  "^wiko,.*":
+    description: Wiko SAS
  "^wiligear,.*":
    description: Wiligear, Ltd.
  "^willsemi,.*":
--- a/1
+++ b/1
@@ -2990,7 +2990,6 @@ S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
 F:	Documentation/devicetree/bindings/arm/marvell/
 F:	arch/arm/boot/dts/marvell/armada*
-F:	arch/arm/boot/dts/marvell/db-falcon*
 F:	arch/arm/boot/dts/marvell/kirkwood*
 F:	arch/arm/configs/mvebu_*_defconfig
 F:	arch/arm/mach-mvebu/
--- a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi
@@ -234,7 +234,7 @@
 				reg = <0x0c 0x04>;
 				#clock-cells = <0>;
 				lock-offset = <0x20>;
-				vco-offset = <0x0C>;
+				vco-offset = <0x0c>;
 				clocks = <&xtal24mhz>;
 			};
 			oscclk1: clock-controller@10 {
--- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts
@@ -260,7 +260,7 @@
 				reg = <0x0c 0x04>;
 				#clock-cells = <0>;
 				lock-offset = <0x20>;
-				vco-offset = <0x0C>;
+				vco-offset = <0x0c>;
 				clocks = <&xtal24mhz>;
 			};
 			oscclk1: clock-controller@10 {
--- a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts
@@ -343,7 +343,7 @@
 				reg = <0x0c 0x04>;
 				#clock-cells = <0>;
 				lock-offset = <0x20>;
-				vco-offset = <0x0C>;
+				vco-offset = <0x0c>;
 				clocks = <&xtal24mhz>;
 			};
 			oscclk1: clock-controller@10 {
--- a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi
@@ -256,7 +256,7 @@
 				reg = <0x0c 0x04>;
 				#clock-cells = <0>;
 				lock-offset = <0x20>;
-				vco-offset = <0x0C>;
+				vco-offset = <0x0c>;
 				clocks = <&xtal24mhz>;
 			};
 			oscclk1: clock-controller@10 {
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -12,9 +12,11 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-asrock-altrad8.dtb \
 	aspeed-bmc-asrock-e3c246d4i.dtb \
 	aspeed-bmc-asrock-e3c256d4i.dtb \
+	aspeed-bmc-asrock-paul-ipmi-card.dtb \
 	aspeed-bmc-asrock-romed8hm3.dtb \
 	aspeed-bmc-asrock-spc621d8hm3.dtb \
 	aspeed-bmc-asrock-x570d4u.dtb \
+	aspeed-bmc-asus-kommando-ipmi-card.dtb \
 	aspeed-bmc-asus-x4tf.dtb \
 	aspeed-bmc-bytedance-g220a.dtb \
 	aspeed-bmc-delta-ahe50dc.dtb \
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-paul-ipmi-card.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-paul-ipmi-card.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 Anirudh Srinivasan
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/{
+	model = "ASRock Paul IPMI Card";
+	compatible = "asrock,ast2500-paul-ipmi-card", "aspeed,ast2500";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-fan-1 {
+			gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;
+			label = "fan1_red";
+			default-state = "off";
+		};
+
+		led-fan-2 {
+			gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>;
+			label = "fan2_red";
+			default-state = "off";
+		};
+
+		led-fault {
+			gpios = <&gpio ASPEED_GPIO(Y, 3) GPIO_ACTIVE_LOW>;
+			label = "panic_red";
+			panic-indicator;
+			default-state = "off";
+		};
+
+		led-heartbeat {
+			gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+			label = "heartbeat_green";
+			linux,default-trigger = "timer";
+		};
+	};
+
+	memory@80000000 {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		video_engine_memory: video {
+			size = <0x02000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+	};
+};
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-max-frequency = <50000000>; /* 50 MHz */
+#include "openbmc-flash-layout.dtsi"
+	};
+};
+
+&gpio {
+	status = "okay";
+	gpio-line-names =
+		/*  A */ "", "", "", "", "", "", "", "",
+		/*  B */ "", "", "", "", "", "", "", "",
+		/*  C */ "", "", "", "", "", "", "", "",
+		/*  D */ "", "BMC_PWRBTN", "", "BMC_RESETCON", "", "", "", "",
+		/*  E */ "", "", "", "", "", "", "", "",
+		/*  F */ "", "", "", "", "", "", "", "",
+		/*  G */ "", "", "", "", "", "", "", "",
+		/*  H */ "", "", "", "", "", "", "BMC_LED1", "",
+		/*  I */ "", "", "", "", "", "", "", "",
+		/*  J */ "", "", "", "", "", "", "", "",
+		/*  K */ "", "", "", "", "", "", "", "",
+		/*  L */ "", "", "", "", "", "", "", "",
+		/*  M */ "", "", "", "", "", "", "", "",
+		/*  N */ "", "", "", "", "", "", "", "",
+		/*  O */ "", "", "", "", "", "", "", "",
+		/*  P */ "", "", "", "", "", "", "", "",
+		/*  Q */ "", "", "", "", "", "", "", "",
+		/*  R */ "", "", "", "", "", "", "", "",
+		/*  S */ "", "", "", "", "", "", "", "",
+		/*  T */ "", "", "", "", "", "", "", "",
+		/*  U */ "", "", "", "", "", "", "", "",
+		/*  V */ "", "", "", "", "", "", "", "",
+		/*  W */ "", "", "", "", "", "", "", "",
+		/*  X */ "", "", "", "", "", "PCIE_STNDBY", "", "",
+		/*  Y */ "", "", "", "SYSTEM_ERR_LED", "", "", "", "",
+		/*  Z */ "", "", "", "", "", "", "", "",
+		/* AA */ "FAN_1_LED", "FAN_2_LED", "", "", "", "", "", "",
+		/* AB */ "", "", "", "", "", "", "", "",
+		/* AC */ "", "", "", "", "", "", "", "";
+};
+
+&mac0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	status = "okay";
+	memory-region = <&video_engine_memory>;
+};
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 Anirudh Srinivasan
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include "aspeed-g6-pinctrl.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "Asus Kommando IPMI Expansion Card";
+	compatible = "asus,ast2600-kommando-ipmi-card", "aspeed,ast2600";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = "serial4:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-fault {
+			gpios = <&gpio1 ASPEED_GPIO(C, 5) GPIO_ACTIVE_HIGH>;
+			label = "panic_amber";
+			panic-indicator;
+			default-state = "off";
+		};
+
+		led-heartbeat {
+			gpios = <&gpio0 ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>;
+			label = "heartbeat_green";
+			linux,default-trigger = "timer";
+		};
+
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		video_engine_memory: video {
+			size = <0x04000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+	};
+};
+
+&fmc {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+};
+
+&gpio0 {
+	gpio-line-names =
+	/*A0 0*/	"", "", "", "", "", "", "", "BMC_HBLED",
+	/*B0 8*/	"", "", "", "", "", "", "", "",
+	/*C0 16*/	"", "", "", "", "", "", "", "",
+	/*D0 24*/	"", "", "", "", "", "", "", "",
+	/*E0 32*/	"", "", "", "", "", "", "", "",
+	/*F0 40*/	"", "", "", "", "", "", "", "",
+	/*G0 48*/	"", "", "", "", "", "", "", "",
+	/*H0 56*/	"", "", "", "", "", "", "", "",
+	/*I0 64*/	"", "", "", "BMC_RSTBTN", "", "", "", "",
+	/*J0 72*/	"", "", "", "", "", "", "", "",
+	/*K0 80*/	"", "", "", "", "", "", "", "",
+	/*L0 88*/	"", "", "", "", "", "", "", "",
+	/*M0 96*/	"", "", "", "", "", "", "", "",
+	/*N0 104*/	"", "", "", "", "", "", "", "",
+	/*O0 112*/	"", "", "", "", "", "", "", "",
+	/*P0 120*/	"", "", "", "", "", "", "", "",
+	/*Q0 128*/	"", "", "", "", "", "", "", "",
+	/*R0 136*/	"", "", "", "", "", "", "", "",
+	/*S0 144*/	"", "", "", "", "", "", "", "",
+	/*T0 152*/	"", "", "", "", "", "", "", "",
+	/*U0 160*/	"", "", "", "", "", "", "", "",
+	/*V0 168*/	"", "", "", "", "BMC_PWRBTN", "", "MB_S0_DETECT", "",
+	/*W0 176*/	"", "", "", "", "", "", "", "",
+	/*X0 184*/	"", "", "", "", "", "", "", "",
+	/*Y0 192*/	"", "", "", "", "", "", "", "",
+	/*Z0 200*/	"", "", "", "", "", "", "", "";
+};
+
+&gpio1 {
+	gpio-line-names =
+	/*18A0 0*/  "","","","","","","","",
+	/*18B0 8*/  "","","","","","","","",
+	/*18C0 16*/ "","","","","","BMC_MLED","","",
+	/*18D0 24*/ "","","","","","","","",
+	/*18E0 32*/ "","","","","","","","";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	status = "okay";
+	memory-region = <&video_engine_memory>;
+};
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -300,6 +300,12 @@
 &i2c0 {
 	status = "okay";

+	eeprom@50 {
+		compatible = "atmel,24c2048";
+		reg = <0x50>;
+		pagesize = <128>;
+	};
+
 	i2c-mux@70 {
 		compatible = "nxp,pca9546";
 		reg = <0x70>;
@@ -334,6 +340,12 @@
 &i2c1 {
 	status = "okay";

+	eeprom@50 {
+		compatible = "atmel,24c2048";
+		reg = <0x50>;
+		pagesize = <128>;
+	};
+
 	i2c-mux@70 {
 		compatible = "nxp,pca9546";
 		reg = <0x70>;
@@ -802,6 +814,16 @@
 			reg = <7>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			nfc@28 {
+				compatible = "nxp,nxp-nci-i2c";
+				reg = <0x28>;
+
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
+
+				enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
+			};
 		};
 	};
 };
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts
@@ -67,6 +67,7 @@
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <1>;
 		status = "okay";
+		#include "openbmc-flash-layout-128-alt.dtsi"
 	};
 };

--- a/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128-alt.dtsi
+++ b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128-alt.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+partitions {
+	compatible = "fixed-partitions";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	u-boot@0 {
+		reg = <0x0 0xe0000>; // 896KB
+		label = "alt-u-boot";
+	};
+
+	u-boot-env@e0000 {
+		reg = <0xe0000 0x20000>; // 128KB
+		label = "alt-u-boot-env";
+	};
+
+	kernel@100000 {
+		reg = <0x100000 0x900000>; // 9MB
+		label = "alt-kernel";
+	};
+
+	rofs@a00000 {
+		reg = <0xa00000 0x5600000>; // 86MB
+		label = "alt-rofs";
+	};
+
+	rwfs@6000000 {
+		reg = <0x6000000 0x2000000>; // 32MB
+		label = "alt-rwfs";
+	};
+};
--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
@@ -95,7 +95,10 @@
 	axi@18000000 {
 		compatible = "brcm,bus-axi";
 		reg = <0x18000000 0x1000>;
-		ranges = <0x00000000 0x18000000 0x00100000>;
+		ranges = <0x00000000 0x18000000 0x00100000>,
+			 <0x08000000 0x08000000 0x08000000>,
+			 <0x20000000 0x20000000 0x08000000>,
+			 <0x28000000 0x28000000 0x08000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;

@@ -182,24 +185,75 @@
 		};

 		pcie0: pcie@12000 {
+			compatible = "brcm,iproc-pcie";
 			reg = <0x00012000 0x1000>;
+			ranges = <0x82000000 0 0x08000000  0x08000000  0 0x08000000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";

+			#interrupt-cells = <1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
+
+			pcie_bridge0: pcie@0 {
+				device_type = "pci";
+				reg = <0x0000 0 0 0 0>;
+				bus-range = <0x00 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};

 		pcie1: pcie@13000 {
+			compatible = "brcm,iproc-pcie";
 			reg = <0x00013000 0x1000>;
+			ranges = <0x82000000 0 0x20000000  0x20000000  0 0x08000000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";

+			#interrupt-cells = <1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
+
+			pcie_bridge1: pcie@0 {
+				device_type = "pci";
+				reg = <0x0000 0 0 0 0>;
+				bus-range = <0x00 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};

 		pcie2: pcie@14000 {
+			compatible = "brcm,iproc-pcie";
 			reg = <0x00014000 0x1000>;
+			ranges = <0x82000000 0 0x28000000  0x28000000  0 0x08000000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";

+			#interrupt-cells = <1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
+
+			pcie_bridge2: pcie@0 {
+				device_type = "pci";
+				reg = <0x0000 0 0 0 0>;
+				bus-range = <0x00 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};

 		usb2: usb2@21000 {
@@ -479,7 +533,7 @@
 	};

 	nand_controller: nand-controller@18028000 {
-		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
+		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
 		reg-names = "nand", "iproc-idm", "iproc-ext";
 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
--- a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi
@@ -141,9 +141,10 @@
 			interrupts = <1 10>;
 		};

-		vc4: gpu {
-			compatible = "brcm,bcm2835-vc4";
-		};
+	};
+
+	vc4: gpu {
+		compatible = "brcm,bcm2835-vc4";
 	};
 };

--- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi
@@ -1,8 +1,8 @@
 #include <dt-bindings/power/raspberrypi-power.h>

 / {
-	soc {
-		firmware: firmware {
+	firmware {
+		firmware: rpi-firmware {
 			compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
 			mboxes = <&mailbox>;

@@ -10,14 +10,16 @@
 				compatible = "raspberrypi,firmware-clocks";
 				#clock-cells = <1>;
 			};
-		};

-		power: power {
-			compatible = "raspberrypi,bcm2835-power";
-			firmware = <&firmware>;
-			#power-domain-cells = <1>;
+			power: power {
+				compatible = "raspberrypi,bcm2835-power";
+				firmware = <&firmware>;
+				#power-domain-cells = <1>;
+			};
 		};
+	};

+	soc {
 		vchiq: mailbox@7e00b840 {
 			compatible = "brcm,bcm2835-vchiq";
 			reg = <0x7e00b840 0x3c>;
--- a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts
+++ b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts
@@ -5,6 +5,8 @@

 /dts-v1/;

+#include <dt-bindings/leds/common.h>
+
 #include "bcm4709.dtsi"
 #include "bcm5301x-nand-cs0-bch8.dtsi"

@@ -25,6 +27,10 @@
 	nvram@1c080000 {
 		compatible = "brcm,nvram";
 		reg = <0x1c080000 0x180000>;
+
+		et2macaddr: et2macaddr {
+			#nvmem-cell-cells = <1>;
+		};
 	};

 	gpio-keys {
@@ -36,18 +42,69 @@
 			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
 		};

+		button-rfkill {
+			label = "WiFi";
+			linux,code = <KEY_RFKILL>;
+			gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+		};
+
 		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_WLAN;
+			gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "rfkill-none";
+		};
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_USB;
+			function-enumerator = <2>;
+			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "usbport";
+			trigger-sources = <&ohci_port2>, <&ehci_port2>;
+		};
+
+		led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_USB;
+			function-enumerator = <3>;
+			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "usbport";
+			trigger-sources = <&ohci_port1>, <&ehci_port1>,
+					  <&xhci_port1>;
+		};
+
+		led-3 {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+	};
 };

 &usb3_phy {
 	status = "okay";
 };

+&usb2 {
+	vcc-gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+	vcc-gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
+};
+
 &srab {
 	status = "okay";

@@ -70,6 +127,9 @@

 		port@4 {
 			label = "wan";
+
+			nvmem-cells = <&et2macaddr 1>;
+			nvmem-cell-names = "mac-address";
 		};

 		port@5 {
@@ -85,3 +145,43 @@
 		};
 	};
 };
+
+&nandcs {
+	partitions {
+		compatible = "linksys,ns-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "boot";
+			reg = <0x0000000 0x0080000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "nvram";
+			reg = <0x080000 0x0100000>;
+		};
+
+		partition@180000 {
+			label = "devinfo";
+			reg = <0x0180000 0x080000>;
+			read-only;
+		};
+
+		partition@200000 {
+			reg = <0x0200000 0x02800000>;
+			compatible = "linksys,ns-firmware", "brcm,trx";
+		};
+
+		partition@2a00000 {
+			reg = <0x02a00000 0x02800000>;
+			compatible = "linksys,ns-firmware", "brcm,trx";
+		};
+
+		partition@5200000 {
+			label = "system";
+			reg = <0x05200000 0x02e00000>;
+		};
+	};
+};
--- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
@@ -126,66 +126,53 @@
 	};
 };

-&pcie0 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-
-	bridge@0,0,0 {
+&pcie_bridge0 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
 		reg = <0x0000 0 0 0 0>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		wifi@0,1,0 {
-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-			reg = <0x0000 0 0 0 0>;
-			ieee80211-freq-limit = <5735000 5835000>;
-			brcm,ccode-map = "JP-JP-78", "US-Q2-86";
-		};
+		ieee80211-freq-limit = <5735000 5835000>;
+		brcm,ccode-map = "JP-JP-78", "US-Q2-86";
 	};
 };

-&pcie1 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-
-	bridge@1,0,0 {
+&pcie_bridge1 {
+	pcie@0,0 {
+		device_type = "pci";
 		reg = <0x0000 0 0 0 0>;
+		bus-range = <0x01 0xff>;

 		#address-cells = <3>;
 		#size-cells = <2>;
+		ranges;

-		bridge@1,1,0 {
-			reg = <0x0000 0 0 0 0>;
+		pcie@1,0 {
+			device_type = "pci";
+			reg = <0x800 0 0 0 0>;

 			#address-cells = <3>;
 			#size-cells = <2>;
+			ranges;

-			bridge@1,0 {
-				reg = <0x800 0 0 0 0>;
-
-				#address-cells = <3>;
-				#size-cells = <2>;
-
-				wifi@0,0 {
-					compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-					reg = <0x0000 0 0 0 0>;
-					brcm,ccode-map = "JP-JP-78", "US-Q2-86";
-				};
+			wifi@0,0 {
+				compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+				reg = <0x0000 0 0 0 0>;
+				brcm,ccode-map = "JP-JP-78", "US-Q2-86";
 			};
+		};

-			bridge@1,2,2 {
-				reg = <0x1000 0 0 0 0>;
+		pcie@2,0 {
+			device_type = "pci";
+			reg = <0x1000 0 0 0 0>;

-				#address-cells = <3>;
-				#size-cells = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;

-				wifi@1,4,0 {
-					compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-					reg = <0x0000 0 0 0 0>;
-					ieee80211-freq-limit = <5170000 5730000>;
-					brcm,ccode-map = "JP-JP-78", "US-Q2-86";
-				};
+			wifi@0,0 {
+				compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
+				reg = <0x0000 0 0 0 0>;
+				ieee80211-freq-limit = <5170000 5730000>;
+				brcm,ccode-map = "JP-JP-78", "US-Q2-86";
 			};
 		};
 	};
--- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi
@@ -18,6 +18,10 @@
 	nvram@1c080000 {
 		compatible = "brcm,nvram";
 		reg = <0x1c080000 0x00180000>;
+
+		et0macaddr: et0macaddr {
+			#nvmem-cell-cells = <1>;
+		};
 	};

 	gpio-keys {
@@ -143,6 +147,9 @@

 		port@4 {
 			label = "wan";
+
+			nvmem-cells = <&et0macaddr 1>;
+			nvmem-cell-names = "mac-address";
 		};

 		port@5 {
--- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts
+++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts
@@ -127,6 +127,9 @@
 	ports {
 		port@0 {
 			label = "wan";
+
+			nvmem-cells = <&et1macaddr 1>;
+			nvmem-cell-names = "mac-address";
 		};

 		port@1 {
--- a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts
@@ -25,6 +25,10 @@
 	nvram@1c080000 {
 		compatible = "brcm,nvram";
 		reg = <0x1c080000 0x100000>;
+
+		et2macaddr: et2macaddr {
+			#nvmem-cell-cells = <1>;
+		};
 	};

 	gpio-keys {
@@ -230,6 +234,9 @@

 		port@4 {
 			label = "wan";
+
+			nvmem-cells = <&et2macaddr 1>;
+			nvmem-cell-names = "mac-address";
 		};

 		port@5 {
--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts
+++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts
@@ -65,39 +65,19 @@
 };


-&pcie0 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-
-	bridge@0,0 {
+&pcie_bridge0 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
 		reg = <0x0000 0 0 0 0>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		wifi@0,0 {
-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-			reg = <0x0000 0 0 0 0>;
-			brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
-		};
+		brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
 	};
 };

-&pcie1 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-
-	bridge@0,0 {
+&pcie_bridge1 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
 		reg = <0x0000 0 0 0 0>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		wifi@0,0 {
-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-			reg = <0x0000 0 0 0 0>;
-			brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
-		};
+		brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825";
 	};
 };

--- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts
@@ -81,39 +81,19 @@
 	nvmem-cell-names = "mac-address";
 };

-&pcie0 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-
-	bridge@0,0 {
+&pcie_bridge0 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
 		reg = <0x0000 0 0 0 0>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		wifi@0,0 {
-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-			reg = <0x0000 0 0 0 0>;
-			brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
-		};
+		brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
 	};
 };

-&pcie1 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-
-	bridge@0,0 {
+&pcie_bridge1 {
+	wifi@0,0 {
+		compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
 		reg = <0x0000 0 0 0 0>;
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		wifi@0,0 {
-			compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
-			reg = <0x0000 0 0 0 0>;
-			brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
-		};
+		brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930";
 	};
 };

--- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
@@ -312,12 +312,21 @@
 			reg = <0x8000 0x50>;
 		};

+		i2c0: i2c@3e00 {
+			compatible = "brcm,brcmper-i2c";
+			reg = <0x3e00 0x60>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		pl081_dma: dma-controller@d000 {
 			compatible = "arm,pl081", "arm,primecell";
 			// The magic B105F00D info is missing
 			arm,primecell-periphid = <0x00041081>;
 			reg = <0xd000 0x1000>;
-			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 			memcpy-burst-size = <256>;
 			memcpy-bus-width = <32>;
 			clocks = <&periph_clk>;
--- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
@@ -97,7 +97,7 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges = <0 0xfffe8000 0x8000>;
+		ranges = <0 0xfffe8000 0x20000>;

 		/* GPIOs 0 .. 31 */
 		gpio0: gpio@100 {
@@ -197,5 +197,14 @@
 				reg = <0>;
 			};
 		};
+
+		i2c0: i2c@3e00 {
+			compatible = "brcm,brcmper-i2c";
+			reg = <0x3e00 0x60>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };
--- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
@@ -242,6 +242,15 @@
 			status = "disabled";
 		};

+		i2c0: i2c@2100 {
+			compatible = "brcm,brcmper-i2c";
+			reg = <0x2100 0x60>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		pl081_dma: dma-controller@59000 {
 			compatible = "arm,pl081", "arm,primecell";
 			// The magic B105F00D info is missing
--- a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
@@ -240,6 +240,15 @@
 			};
 		};

+		i2c0: i2c@2100 {
+			compatible = "brcm,brcmper-i2c";
+			reg = <0x2100 0x60>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		leds: led-controller@3000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -278,5 +287,14 @@
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
+
+		i2c1: i2c@5a800 {
+			compatible = "brcm,brcmper-i2c";
+			reg = <0x5a800 0x60>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };
--- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
@@ -239,12 +239,21 @@
 			};
 		};

+		i2c0: i2c@2100 {
+			compatible = "brcm,brcmper-i2c";
+			reg = <0x2100 0x60>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		pl081_dma: dma-controller@11000 {
 			compatible = "arm,pl081", "arm,primecell";
 			// The magic B105F00D info is missing
 			arm,primecell-periphid = <0x00041081>;
 			reg = <0x11000 0x1000>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			memcpy-burst-size = <256>;
 			memcpy-bus-width = <32>;
 			clocks = <&periph_clk>;
--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi
@@ -328,7 +328,7 @@

 	efuse: efuse@10206000 {
 		compatible = "mediatek,mt7623-efuse",
-			     "mediatek,mt8173-efuse";
+			     "mediatek,efuse";
 		reg = <0 0x10206000 0 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -75,8 +75,6 @@
 		ranges;

 		usb0: gadget@500000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
 			compatible = "microchip,sam9x60-udc";
 			reg = <0x00500000 0x100000
 				0xf803c000 0x400>;
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -67,6 +67,11 @@
 		#size-cells = <1>;
 	};

+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
@@ -278,6 +283,41 @@
 			status = "disabled";
 		};

+		xlcdc: lcd-controller@e1400000 {
+			compatible = "microchip,sama7d65-xlcdc";
+			reg = <0xe1400000 0x2000>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>, <&clk32k 1>;
+			clock-names = "periph_clk", "sys_clk", "slow_clk";
+			status = "disabled";
+
+			display-controller {
+				compatible = "atmel,hlcdc-display-controller";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			pwm {
+				compatible = "atmel,hlcdc-pwm";
+				#pwm-cells = <3>;
+			};
+		};
+
+		lvdsc: lvds-controller@e1408000 {
+			compatible = "microchip,sama7d65-lvds", "microchip,sam9x75-lvds";
+			reg = <0xe1408000 0x100>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 104>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
 		aes: crypto@e1600000 {
 			compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes";
 			reg = <0xe1600000 0x100>;
--- a/arch/arm/boot/dts/nvidia/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts
@@ -43,7 +43,9 @@
 				compatible = "lg,ld070wx3-sl01";
 				reg = <0>;

-				power-supply = <&vdd_lcd>;
+				vdd-supply = <&avdd_lcd>;
+				vcc-supply = <&dvdd_lcd>;
+
 				backlight = <&backlight>;
 			};
 		};
@@ -101,11 +103,10 @@
 						regulator-boot-on;
 					};

-					smps6 {
+					avdd_lcd: smps6 {
 						regulator-name = "va-lcd-hv";
-						regulator-min-microvolt = <3000000>;
-						regulator-max-microvolt = <3000000>;
-						regulator-always-on;
+						regulator-min-microvolt = <3160000>;
+						regulator-max-microvolt = <3160000>;
 						regulator-boot-on;
 					};

@@ -325,7 +326,7 @@
 		regulator-boot-on;
 	};

-	vdd_lcd: regulator-lcd {
+	dvdd_lcd: regulator-lcd {
 		compatible = "regulator-fixed";
 		regulator-name = "VD_LCD_1V8";
 		regulator-min-microvolt = <1800000>;
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/nvidia,tegra114-car.h>
 #include <dt-bindings/soc/tegra-pmc.h>
+#include <dt-bindings/thermal/tegra114-soctherm.h>

 / {
 	compatible = "nvidia,tegra114";
@@ -258,6 +259,8 @@
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+
+		nvidia,external-memory-controller = <&emc>;
 	};

 	flow-controller@60007000 {
@@ -311,6 +314,18 @@
 		reg = <0x6000c000 0x150>;
 	};

+	actmon: actmon@6000c800 {
+		compatible = "nvidia,tegra114-actmon";
+		reg = <0x6000c800 0x400>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_ACTMON>,
+			 <&tegra_car TEGRA114_CLK_EMC>;
+		clock-names = "actmon", "emc";
+		resets = <&tegra_car TEGRA114_CLK_ACTMON>;
+		reset-names = "actmon";
+		#cooling-cells = <2>;
+	};
+
 	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
@@ -642,6 +657,16 @@
 		#iommu-cells = <1>;
 	};

+	emc: external-memory-controller@7001b000 {
+		compatible = "nvidia,tegra114-emc";
+		reg = <0x7001b000 0x800>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_EMC>;
+		clock-names = "emc";
+
+		nvidia,memory-controller = <&mc>;
+	};
+
 	hda@70030000 {
 		compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda";
 		reg = <0x70030000 0x10000>;
@@ -751,6 +776,46 @@
 		};
 	};

+	soctherm: thermal-sensor@700e2000 {
+		compatible = "nvidia,tegra114-soctherm";
+		reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
+		      <0x60006000 0x400>; /* CAR reg_base */
+		reg-names = "soctherm-reg", "car-reg";
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "thermal", "edp";
+		clocks = <&tegra_car TEGRA114_CLK_TSENSOR>,
+			 <&tegra_car TEGRA114_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+
+		assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>,
+				  <&tegra_car TEGRA114_CLK_SOC_THERM>;
+		assigned-clock-rates = <500000>, <51000000>;
+
+		assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>,
+					 <&tegra_car TEGRA114_CLK_PLL_P>;
+
+		#thermal-sensor-cells = <1>;
+
+		throttle-cfgs {
+			throttle_heavy: heavy {
+				nvidia,priority = <100>;
+				nvidia,cpu-throt-percent = <80>;
+				nvidia,gpu-throt-level = <TEGRA114_SOCTHERM_THROT_LEVEL_HIGH>;
+				#cooling-cells = <2>;
+			};
+
+			throttle_light: light {
+				nvidia,priority = <80>;
+				nvidia,cpu-throt-percent = <50>;
+				nvidia,gpu-throt-level = <TEGRA114_SOCTHERM_THROT_LEVEL_MED>;
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
 	mipi: mipi@700e3000 {
 		compatible = "nvidia,tegra114-mipi";
 		reg = <0x700e3000 0x100>;
@@ -921,24 +986,28 @@
 			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
 			/* FIXME: what's the actual transition time? */
 			clock-latency = <300000>;
+			#cooling-cells = <2>;
 		};

 		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <1>;
+			#cooling-cells = <2>;
 		};

 		cpu2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <2>;
+			#cooling-cells = <2>;
 		};

 		cpu3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <3>;
+			#cooling-cells = <2>;
 		};
 	};

@@ -951,6 +1020,158 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	};

+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA114_SOCTHERM_SENSOR_CPU>;
+
+			trips {
+				cpu-shutdown-trip {
+					temperature = <102000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+
+				cpu_throttle_trip: cpu-throttle-trip {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				cpu_balanced_trip: cpu-balanced-trip {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_throttle_trip>;
+					cooling-device = <&throttle_heavy 1 1>;
+				};
+
+				map1 {
+					trip = <&cpu_balanced_trip>;
+					cooling-device = <&throttle_light 1 1>;
+				};
+			};
+		};
+
+		mem-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA114_SOCTHERM_SENSOR_MEM>;
+
+			trips {
+				mem-shutdown-trip {
+					temperature = <102000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+
+				mem_throttle_trip: mem-throttle-trip {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				mem_balanced_trip: mem-balanced-trip {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				/*
+				 * There are currently no cooling maps,
+				 * because there are no cooling devices.
+				 */
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA114_SOCTHERM_SENSOR_GPU>;
+
+			trips {
+				gpu-shutdown-trip {
+					temperature = <102000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+
+				gpu_throttle_trip: gpu-throttle-trip {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				gpu_balanced_trip: gpu-balanced-trip {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu_throttle_trip>;
+					cooling-device = <&throttle_heavy 1 1>;
+				};
+
+				map1 {
+					trip = <&gpu_balanced_trip>;
+					cooling-device = <&throttle_light 1 1>;
+				};
+			};
+		};
+
+		pllx-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+
+			thermal-sensors =
+				<&soctherm TEGRA114_SOCTHERM_SENSOR_PLLX>;
+
+			trips {
+				pllx-shutdown-trip {
+					temperature = <102000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+
+				pllx_throttle_trip: pllx-throttle-trip {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				pllx_balanced_trip: pllx-balanced-trip {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				/*
+				 * There are currently no cooling maps,
+				 * because there are no cooling devices.
+				 */
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts =
--- a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts
@@ -706,6 +706,14 @@
 		enable-active-high;
 	};

+	rfkill {
+		compatible = "rfkill-gpio";
+		label = "wifi_rfkill";
+		radio-type = "wlan";
+		reset-gpios = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>;
+	};
+
 	sound {
 		compatible = "nvidia,tegra-audio-alc5632-paz00",
 			"nvidia,tegra-audio-alc5632";
--- a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts
+++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts
@@ -62,8 +62,11 @@
 			pll-supply = <&vdd_1v8_vio>;
 			vdd-supply = <&vdd_3v3_sys>;

-			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
-			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			port {
+				hdmi_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
 		};
 	};

@@ -2174,6 +2177,20 @@
 		clock-output-names = "pmic-oscillator";
 	};

+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "d";
+
+		hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+		ddc-i2c-bus = <&hdmi_ddc>;
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_out>;
+			};
+		};
+	};
+
 	cpus {
 		cpu0: cpu@0 {
 			cpu-supply = <&vdd_cpu>;
--- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts
+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts
@@ -116,6 +116,29 @@
 		};
 	};

+	spi@7000dc00 {
+		dsi@2 {
+			/*
+			 * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
+			 */
+			panel@1 {
+				compatible = "jdi,dx12d100vm0eaa", "renesas,r69328";
+				reg = <1>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+				vdd-supply = <&vcc_3v0_lcd>;
+				vddio-supply = <&iovcc_1v8_lcd>;
+
+				port {
+					panel_input: endpoint {
+						remote-endpoint = <&bridge_output>;
+					};
+				};
+			};
+		};
+	};
+
 	memory-controller@7000f000 {
 		emc-timings-0 {
 			/* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */
--- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
@@ -109,6 +109,39 @@
 				syna,clip-x-high = <1535>;
 				syna,clip-y-high = <2047>;
 			};
+
+			rmi4-f1a@1a {
+				reg = <0x1a>;
+
+				linux,keycodes = <KEY_BACK KEY_HOME KEY_MENU KEY_SEARCH>;
+			};
+		};
+	};
+
+	spi@7000dc00 {
+		dsi@2 {
+			/*
+			 * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
+			 */
+			panel@1 {
+				compatible = "koe,tx13d100vm0eaa", "renesas,r61307";
+				reg = <1>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+				renesas,gamma = <3>;
+				renesas,column-inversion;
+				renesas,contrast;
+
+				vcc-supply = <&vcc_3v0_lcd>;
+				iovcc-supply = <&iovcc_1v8_lcd>;
+
+				port {
+					panel_input: endpoint {
+						remote-endpoint = <&bridge_output>;
+					};
+				};
+			};
 		};
 	};

--- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi
@@ -20,6 +20,8 @@
 		rtc0 = &pmic;
 		rtc1 = "/rtc@7000e000";

+		display0 = &lcd;
+
 		serial0 = &uartd; /* Console */
 		serial1 = &uartc; /* Bluetooth */
 		serial2 = &uartb; /* GPS */
@@ -71,6 +73,21 @@
 		};
 	};

+	host1x@50000000 {
+		lcd: dc@54200000 {
+			rgb {
+				status = "okay";
+
+				port {
+					dpi_output: endpoint {
+						remote-endpoint = <&bridge_input>;
+						bus-width = <24>;
+					};
+				};
+			};
+		};
+	};
+
 	vde@6001a000 {
 		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
 		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
@@ -1053,6 +1070,38 @@
 				syna,clip-y-low = <0>;
 			};
 		};
+
+		max14526: muic@44 {
+			compatible = "maxim,max14526";
+			reg = <0x44>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_EDGE_FALLING>;
+
+			muic_con: connector {
+				compatible = "usb-b-connector";
+				label = "micro-USB";
+				type = "micro";
+			};
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				muic_to_charger: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&charger_input>;
+				};
+			};
+		};
+
+		tsc2007: adc@48 {
+			compatible = "ti,tsc2007";
+			reg = <0x48>;
+
+			ti,x-plate-ohms = <1>;
+			#io-channel-cells = <1>;
+		};
 	};

 	cam_i2c: i2c@7000c500 {
@@ -1309,6 +1358,22 @@
 			};
 		};

+		max8971: charger@35 {
+			compatible = "maxim,max8971";
+			reg = <0x35>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(J, 2) IRQ_TYPE_LEVEL_LOW>;
+
+			monitored-battery = <&battery>;
+
+			port {
+				charger_input: endpoint {
+					remote-endpoint = <&muic_to_charger>;
+				};
+			};
+		};
+
 		fuel-gauge@36 {
 			compatible = "maxim,max17043";
 			reg = <0x36>;
@@ -1317,6 +1382,10 @@
 			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>;

 			monitored-battery = <&battery>;
+			power-supplies = <&max8971>;
+
+			io-channels = <&tbattery 0>;
+			io-channel-names = "temp";

 			maxim,alert-low-soc-level = <10>;
 			wakeup-source;
@@ -1357,7 +1426,58 @@
 		status = "okay";
 		spi-max-frequency = <25000000>;

-		/* DSI bridge */
+		dsi@2 {
+			compatible = "solomon,ssd2825";
+			reg = <2>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spi-max-frequency = <1000000>;
+
+			spi-cpha;
+			spi-cpol;
+
+			reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
+
+			dvdd-supply = <&vdd_1v2_rgb>;
+			avdd-supply = <&vdd_1v2_rgb>;
+			vddio-supply = <&vdd_1v8_vio>;
+
+			solomon,hs-zero-delay-ns = <300>;
+			solomon,hs-prep-delay-ns = <65>;
+
+			clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_3>;
+
+			assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN3>,
+					  <&tegra_pmc TEGRA_PMC_CLK_OUT_3>;
+			assigned-clock-rates = <24000000>;
+
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
+						 <&tegra_car TEGRA30_CLK_EXTERN3>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					bridge_input: endpoint {
+						remote-endpoint = <&dpi_output>;
+						bus-width = <24>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					bridge_output: endpoint {
+						remote-endpoint = <&panel_input>;
+					};
+				};
+			};
+		};
 	};

 	pmc@7000e400 {
@@ -1446,12 +1566,13 @@
 	usb@7d000000 {
 		compatible = "nvidia,tegra30-udc";
 		status = "okay";
-		dr_mode = "peripheral";
+		dr_mode = "otg";
+		extcon = <&max14526>, <&max14526>;
 	};

 	usb-phy@7d000000 {
 		status = "okay";
-		dr_mode = "peripheral";
+		dr_mode = "otg";
 		nvidia,hssync-start-delay = <0>;
 		nvidia,xcvr-lsfslew = <2>;
 		nvidia,xcvr-lsrslew = <2>;
@@ -1617,6 +1738,17 @@
 		vin-supply = <&vdd_3v3_vbat>;
 	};

+	vdd_1v2_rgb: regulator-rgb1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_1v2_rgb";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-boot-on;
+		gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vdd_3v3_vbat>;
+	};
+
 	vcc_3v0_lcd: regulator-lcd3v {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_3v0_lcd";
@@ -1724,7 +1856,43 @@
 					 <&tegra_car TEGRA30_CLK_EXTERN1>;
 	};

+	tbattery: thermal-sensor-battery {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+
+		io-channels = <&tsc2007 4>;
+		io-channel-names = "sensor-channel";
+		#io-channel-cells = <1>;
+
+		temperature-lookup-table = <
+			(-50000) 4100 (-40000) 3980 (-30000) 3815 (-20000) 3610
+			(-10000) 3285        0 2880    10000 2445    20000 1955
+			   30000 1440    40000 1125    50000  840    60000  665
+			   70000  465    80000  350    90000  230   100000  185 >;
+	};
+
 	thermal-zones {
+		battery-thermal {
+			polling-delay-passive = <0>; /* milliseconds */
+			polling-delay = <20000>; /* milliseconds */
+
+			thermal-sensors = <&tbattery>;
+
+			trips {
+				battery-alert {
+					temperature = <55000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				battery-crit {
+					temperature = <60000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
 		/*
 		 * NCT72 has two sensors:
 		 *
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -58,6 +58,31 @@ dtb-$(CONFIG_SOC_IMX53) += \
 	imx53-voipac-bsb.dtb
 imx53-qsb-hdmi-dtbs := imx53-qsb.dtb imx53-qsb-hdmi.dtbo
 imx53-qsrb-hdmi-dtbs := imx53-qsrb.dtb imx53-qsb-hdmi.dtbo
+
+imx6qdl-dhcom-pdk2-overlay-497-200-x12-dtbs := \
+	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtbo
+
+imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \
+	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo
+
+imx6qdl-dhcom-pdk2-overlay-531-100-x21-dtbs := \
+	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtbo
+
+imx6qdl-dhcom-pdk2-overlay-531-100-x22-dtbs := \
+	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtbo
+
+imx6qdl-dhcom-pdk2-overlay-560-200-x12-dtbs := \
+	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtbo
+
+imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
+	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo
+
 dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-alti6p.dtb \
 	imx6dl-apf6dev.dtb \
@@ -179,6 +204,18 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-cubox-i-som-v15.dtb \
 	imx6q-dfi-fs700-m60.dtb \
 	imx6q-dhcom-pdk2.dtb \
+	imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtb \
+	imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtbo \
+	imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \
+	imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \
+	imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtb \
+	imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtbo \
+	imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtb \
+	imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtbo \
+	imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtb \
+	imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtbo \
+	imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \
+	imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \
 	imx6q-display5-tianma-tm070-1280x768.dtb \
 	imx6q-dmo-edmqmx6.dtb \
 	imx6q-dms-ba16.dtb \
--- a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts
@@ -76,60 +76,58 @@
 };

 &iomuxc {
-	imx1-ads {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
-				MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
-				MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
-				MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
-				MX1_PAD_SPI1_SS__GPIO3_15	0x0
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
+			MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
+			MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
+			MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
+			MX1_PAD_SPI1_SS__GPIO3_15	0x0
+		>;
+	};

-		pinctrl_i2c: i2cgrp {
-			fsl,pins = <
-				MX1_PAD_I2C_SCL__I2C_SCL	0x0
-				MX1_PAD_I2C_SDA__I2C_SDA	0x0
-			>;
-		};
+	pinctrl_i2c: i2cgrp {
+		fsl,pins = <
+			MX1_PAD_I2C_SCL__I2C_SCL	0x0
+			MX1_PAD_I2C_SDA__I2C_SDA	0x0
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX1_PAD_UART1_TXD__UART1_TXD	0x0
-				MX1_PAD_UART1_RXD__UART1_RXD	0x0
-				MX1_PAD_UART1_CTS__UART1_CTS	0x0
-				MX1_PAD_UART1_RTS__UART1_RTS	0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX1_PAD_UART1_TXD__UART1_TXD	0x0
+			MX1_PAD_UART1_RXD__UART1_RXD	0x0
+			MX1_PAD_UART1_CTS__UART1_CTS	0x0
+			MX1_PAD_UART1_RTS__UART1_RTS	0x0
+		>;
+	};

-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX1_PAD_UART2_TXD__UART2_TXD	0x0
-				MX1_PAD_UART2_RXD__UART2_RXD	0x0
-				MX1_PAD_UART2_CTS__UART2_CTS	0x0
-				MX1_PAD_UART2_RTS__UART2_RTS	0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX1_PAD_UART2_TXD__UART2_TXD	0x0
+			MX1_PAD_UART2_RXD__UART2_RXD	0x0
+			MX1_PAD_UART2_CTS__UART2_CTS	0x0
+			MX1_PAD_UART2_RTS__UART2_RTS	0x0
+		>;
+	};

-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX1_PAD_A0__A0			0x0
-				MX1_PAD_A16__A16		0x0
-				MX1_PAD_A17__A17		0x0
-				MX1_PAD_A18__A18		0x0
-				MX1_PAD_A19__A19		0x0
-				MX1_PAD_A20__A20		0x0
-				MX1_PAD_A21__A21		0x0
-				MX1_PAD_A22__A22		0x0
-				MX1_PAD_A23__A23		0x0
-				MX1_PAD_A24__A24		0x0
-				MX1_PAD_BCLK__BCLK		0x0
-				MX1_PAD_CS4__CS4		0x0
-				MX1_PAD_DTACK__DTACK		0x0
-				MX1_PAD_ECB__ECB		0x0
-				MX1_PAD_LBA__LBA		0x0
-			>;
-		};
+	pinctrl_weim: weimgrp {
+		fsl,pins = <
+			MX1_PAD_A0__A0			0x0
+			MX1_PAD_A16__A16		0x0
+			MX1_PAD_A17__A17		0x0
+			MX1_PAD_A18__A18		0x0
+			MX1_PAD_A19__A19		0x0
+			MX1_PAD_A20__A20		0x0
+			MX1_PAD_A21__A21		0x0
+			MX1_PAD_A22__A22		0x0
+			MX1_PAD_A23__A23		0x0
+			MX1_PAD_A24__A24		0x0
+			MX1_PAD_BCLK__BCLK		0x0
+			MX1_PAD_CS4__CS4		0x0
+			MX1_PAD_DTACK__DTACK		0x0
+			MX1_PAD_ECB__ECB		0x0
+			MX1_PAD_LBA__LBA		0x0
+		>;
 	};
 };
--- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
@@ -67,56 +67,54 @@
 };

 &iomuxc {
-	imx1-apf9328 {
-		pinctrl_eth: ethgrp {
-			fsl,pins = <
-				MX1_PAD_SIM_SVEN__GPIO2_14	0x0
-			>;
-		};
+	pinctrl_eth: ethgrp {
+		fsl,pins = <
+			MX1_PAD_SIM_SVEN__GPIO2_14	0x0
+		>;
+	};

-		pinctrl_i2c: i2cgrp {
-			fsl,pins = <
-				MX1_PAD_I2C_SCL__I2C_SCL	0x0
-				MX1_PAD_I2C_SDA__I2C_SDA	0x0
-			>;
-		};
+	pinctrl_i2c: i2cgrp {
+		fsl,pins = <
+			MX1_PAD_I2C_SCL__I2C_SCL	0x0
+			MX1_PAD_I2C_SDA__I2C_SDA	0x0
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX1_PAD_UART1_TXD__UART1_TXD	0x0
-				MX1_PAD_UART1_RXD__UART1_RXD	0x0
-				MX1_PAD_UART1_CTS__UART1_CTS	0x0
-				MX1_PAD_UART1_RTS__UART1_RTS	0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX1_PAD_UART1_TXD__UART1_TXD	0x0
+			MX1_PAD_UART1_RXD__UART1_RXD	0x0
+			MX1_PAD_UART1_CTS__UART1_CTS	0x0
+			MX1_PAD_UART1_RTS__UART1_RTS	0x0
+		>;
+	};

-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX1_PAD_UART2_TXD__UART2_TXD	0x0
-				MX1_PAD_UART2_RXD__UART2_RXD	0x0
-				MX1_PAD_UART2_CTS__UART2_CTS	0x0
-				MX1_PAD_UART2_RTS__UART2_RTS	0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX1_PAD_UART2_TXD__UART2_TXD	0x0
+			MX1_PAD_UART2_RXD__UART2_RXD	0x0
+			MX1_PAD_UART2_CTS__UART2_CTS	0x0
+			MX1_PAD_UART2_RTS__UART2_RTS	0x0
+		>;
+	};

-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX1_PAD_A0__A0			0x0
-				MX1_PAD_A16__A16		0x0
-				MX1_PAD_A17__A17		0x0
-				MX1_PAD_A18__A18		0x0
-				MX1_PAD_A19__A19		0x0
-				MX1_PAD_A20__A20		0x0
-				MX1_PAD_A21__A21		0x0
-				MX1_PAD_A22__A22		0x0
-				MX1_PAD_A23__A23		0x0
-				MX1_PAD_A24__A24		0x0
-				MX1_PAD_BCLK__BCLK		0x0
-				MX1_PAD_CS4__CS4		0x0
-				MX1_PAD_DTACK__DTACK		0x0
-				MX1_PAD_ECB__ECB		0x0
-				MX1_PAD_LBA__LBA		0x0
-			>;
-		};
+	pinctrl_weim: weimgrp {
+		fsl,pins = <
+			MX1_PAD_A0__A0			0x0
+			MX1_PAD_A16__A16		0x0
+			MX1_PAD_A17__A17		0x0
+			MX1_PAD_A18__A18		0x0
+			MX1_PAD_A19__A19		0x0
+			MX1_PAD_A20__A20		0x0
+			MX1_PAD_A21__A21		0x0
+			MX1_PAD_A22__A22		0x0
+			MX1_PAD_A23__A23		0x0
+			MX1_PAD_A24__A24		0x0
+			MX1_PAD_BCLK__BCLK		0x0
+			MX1_PAD_CS4__CS4		0x0
+			MX1_PAD_DTACK__DTACK		0x0
+			MX1_PAD_ECB__ECB		0x0
+			MX1_PAD_LBA__LBA		0x0
+		>;
 	};
 };
--- a/arch/arm/boot/dts/nxp/imx/imx1.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx1.dtsi
@@ -202,7 +202,7 @@
 				#clock-cells = <1>;
 			};

-			iomuxc: iomuxc@21c000 {
+			iomuxc: pinmux@21c000 {
 				compatible = "fsl,imx1-iomuxc";
 				reg = <0x0021c000 0x1000>;
 				#address-cells = <1>;
--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
@@ -34,27 +34,25 @@
 };

 &iomuxc {
-	imx25-eukrea-cpuimx25 {
-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
-				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
-				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
-				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
-				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
-				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
-				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
-				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
-				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
+			MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
+			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
+		>;
+	};

-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
-				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
@@ -43,10 +43,8 @@
 };

 &iomuxc {
-	imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
-		pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
-			fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
-		};
+	pinctrl_reg_lcd_3v3: reg_lcd_3v3grp {
+		fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -68,80 +68,78 @@
 };

 &iomuxc {
-	imx25-eukrea-mbimxsd25-baseboard {
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
-				MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
-				MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
-				MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
-			>;
-		};
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
+			MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
+			MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
+			MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
+		>;
+	};

-		pinctrl_esdhc1: esdhc1grp {
-			fsl,pins = <
-				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x400000c0
-				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x400000c0
-				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x400000c0
-				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x400000c0
-				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x400000c0
-				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x400000c0
-			>;
-		};
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			MX25_PAD_SD1_CMD__ESDHC1_CMD		0x400000c0
+			MX25_PAD_SD1_CLK__ESDHC1_CLK		0x400000c0
+			MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x400000c0
+			MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x400000c0
+			MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x400000c0
+			MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x400000c0
+		>;
+	};

-		pinctrl_gpiokeys: gpiokeysgrp {
-			fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
-		};
+	pinctrl_gpiokeys: gpiokeysgrp {
+		fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
+	};

-		pinctrl_gpioled: gpioledgrp {
-			fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
-		};
+	pinctrl_gpioled: gpioledgrp {
+		fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
+	};

-		pinctrl_lcdc: lcdcgrp {
-			fsl,pins = <
-				MX25_PAD_LD0__LD0			0x1
-				MX25_PAD_LD1__LD1			0x1
-				MX25_PAD_LD2__LD2			0x1
-				MX25_PAD_LD3__LD3			0x1
-				MX25_PAD_LD4__LD4			0x1
-				MX25_PAD_LD5__LD5			0x1
-				MX25_PAD_LD6__LD6			0x1
-				MX25_PAD_LD7__LD7			0x1
-				MX25_PAD_LD8__LD8			0x1
-				MX25_PAD_LD9__LD9			0x1
-				MX25_PAD_LD10__LD10			0x1
-				MX25_PAD_LD11__LD11			0x1
-				MX25_PAD_LD12__LD12			0x1
-				MX25_PAD_LD13__LD13			0x1
-				MX25_PAD_LD14__LD14			0x1
-				MX25_PAD_LD15__LD15			0x1
-				MX25_PAD_GPIO_E__LD16			0x1
-				MX25_PAD_GPIO_F__LD17			0x1
-				MX25_PAD_HSYNC__HSYNC			0x80000000
-				MX25_PAD_VSYNC__VSYNC			0x80000000
-				MX25_PAD_LSCLK__LSCLK			0x80000000
-				MX25_PAD_OE_ACD__OE_ACD			0x80000000
-				MX25_PAD_CONTRAST__CONTRAST		0x80000000
-			>;
-		};
+	pinctrl_lcdc: lcdcgrp {
+		fsl,pins = <
+			MX25_PAD_LD0__LD0			0x1
+			MX25_PAD_LD1__LD1			0x1
+			MX25_PAD_LD2__LD2			0x1
+			MX25_PAD_LD3__LD3			0x1
+			MX25_PAD_LD4__LD4			0x1
+			MX25_PAD_LD5__LD5			0x1
+			MX25_PAD_LD6__LD6			0x1
+			MX25_PAD_LD7__LD7			0x1
+			MX25_PAD_LD8__LD8			0x1
+			MX25_PAD_LD9__LD9			0x1
+			MX25_PAD_LD10__LD10			0x1
+			MX25_PAD_LD11__LD11			0x1
+			MX25_PAD_LD12__LD12			0x1
+			MX25_PAD_LD13__LD13			0x1
+			MX25_PAD_LD14__LD14			0x1
+			MX25_PAD_LD15__LD15			0x1
+			MX25_PAD_GPIO_E__LD16			0x1
+			MX25_PAD_GPIO_F__LD17			0x1
+			MX25_PAD_HSYNC__HSYNC			0x80000000
+			MX25_PAD_VSYNC__VSYNC			0x80000000
+			MX25_PAD_LSCLK__LSCLK			0x80000000
+			MX25_PAD_OE_ACD__OE_ACD			0x80000000
+			MX25_PAD_CONTRAST__CONTRAST		0x80000000
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
-				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
-				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
-				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
+			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
+			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
+			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
+		>;
+	};

-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
-				MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
-				MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
-				MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
+			MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
+			MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
+			MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
@@ -130,109 +130,107 @@
 };

 &iomuxc {
-	imx25-pdk {
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX25_PAD_RW__AUD4_TXFS			0xe0
-				MX25_PAD_OE__AUD4_TXC			0xe0
-				MX25_PAD_EB0__AUD4_TXD			0xe0
-				MX25_PAD_EB1__AUD4_RXD			0xe0
-			>;
-		};
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX25_PAD_RW__AUD4_TXFS			0xe0
+			MX25_PAD_OE__AUD4_TXC			0xe0
+			MX25_PAD_EB0__AUD4_TXD			0xe0
+			MX25_PAD_EB1__AUD4_RXD			0xe0
+		>;
+	};

-		pinctrl_can1: can1grp {
-			fsl,pins = <
-				MX25_PAD_GPIO_A__CAN1_TX		0x0
-				MX25_PAD_GPIO_B__CAN1_RX		0x0
-				MX25_PAD_D14__GPIO_4_6 			0x80000000
-			>;
-		};
+	pinctrl_can1: can1grp {
+		fsl,pins = <
+			MX25_PAD_GPIO_A__CAN1_TX		0x0
+			MX25_PAD_GPIO_B__CAN1_RX		0x0
+			MX25_PAD_D14__GPIO_4_6			0x80000000
+		>;
+	};

-		pinctrl_esdhc1: esdhc1grp {
-			fsl,pins = <
-				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
-				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
-				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
-				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
-				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
-				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
-				MX25_PAD_A14__GPIO_2_0			0x80000000
-				MX25_PAD_A15__GPIO_2_1			0x80000000
-			>;
-		};
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			MX25_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
+			MX25_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
+			MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
+			MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
+			MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
+			MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
+			MX25_PAD_A14__GPIO_2_0			0x80000000
+			MX25_PAD_A15__GPIO_2_1			0x80000000
+		>;
+	};

-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
-				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
-				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
-				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
-				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
-				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
-				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
-				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
-				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
-				MX25_PAD_A17__GPIO_2_3			0x80000000
-				MX25_PAD_D12__GPIO_4_8			0x80000000
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
+			MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
+			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
+			MX25_PAD_A17__GPIO_2_3			0x80000000
+			MX25_PAD_D12__GPIO_4_8			0x80000000
+		>;
+	};

-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
-				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
+		>;
+	};

-		pinctrl_kpp: kppgrp {
-			fsl,pins = <
-				MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
-				MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
-				MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
-				MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
-				MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
-				MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
-				MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
-				MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
-			>;
-		};
+	pinctrl_kpp: kppgrp {
+		fsl,pins = <
+			MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
+			MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
+			MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
+			MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
+			MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
+			MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
+			MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
+			MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
+		>;
+	};

-		pinctrl_lcd: lcdgrp {
-			fsl,pins = <
-				MX25_PAD_LD0__LD0		0xe0
-				MX25_PAD_LD1__LD1		0xe0
-				MX25_PAD_LD2__LD2		0xe0
-				MX25_PAD_LD3__LD3		0xe0
-				MX25_PAD_LD4__LD4		0xe0
-				MX25_PAD_LD5__LD5		0xe0
-				MX25_PAD_LD6__LD6		0xe0
-				MX25_PAD_LD7__LD7		0xe0
-				MX25_PAD_LD8__LD8		0xe0
-				MX25_PAD_LD9__LD9		0xe0
-				MX25_PAD_LD10__LD10		0xe0
-				MX25_PAD_LD11__LD11		0xe0
-				MX25_PAD_LD12__LD12		0xe0
-				MX25_PAD_LD13__LD13		0xe0
-				MX25_PAD_LD14__LD14		0xe0
-				MX25_PAD_LD15__LD15		0xe0
-				MX25_PAD_GPIO_E__LD16		0xe0
-				MX25_PAD_GPIO_F__LD17		0xe0
-				MX25_PAD_HSYNC__HSYNC		0xe0
-				MX25_PAD_VSYNC__VSYNC		0xe0
-				MX25_PAD_LSCLK__LSCLK		0xe0
-				MX25_PAD_OE_ACD__OE_ACD		0xe0
-				MX25_PAD_CONTRAST__CONTRAST	0xe0
-			>;
-		};
+	pinctrl_lcd: lcdgrp {
+		fsl,pins = <
+			MX25_PAD_LD0__LD0		0xe0
+			MX25_PAD_LD1__LD1		0xe0
+			MX25_PAD_LD2__LD2		0xe0
+			MX25_PAD_LD3__LD3		0xe0
+			MX25_PAD_LD4__LD4		0xe0
+			MX25_PAD_LD5__LD5		0xe0
+			MX25_PAD_LD6__LD6		0xe0
+			MX25_PAD_LD7__LD7		0xe0
+			MX25_PAD_LD8__LD8		0xe0
+			MX25_PAD_LD9__LD9		0xe0
+			MX25_PAD_LD10__LD10		0xe0
+			MX25_PAD_LD11__LD11		0xe0
+			MX25_PAD_LD12__LD12		0xe0
+			MX25_PAD_LD13__LD13		0xe0
+			MX25_PAD_LD14__LD14		0xe0
+			MX25_PAD_LD15__LD15		0xe0
+			MX25_PAD_GPIO_E__LD16		0xe0
+			MX25_PAD_GPIO_F__LD17		0xe0
+			MX25_PAD_HSYNC__HSYNC		0xe0
+			MX25_PAD_VSYNC__VSYNC		0xe0
+			MX25_PAD_LSCLK__LSCLK		0xe0
+			MX25_PAD_OE_ACD__OE_ACD		0xe0
+			MX25_PAD_CONTRAST__CONTRAST	0xe0
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
-				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
-				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
-				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
+			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
+			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
+			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx25.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi
@@ -195,7 +195,7 @@
 				status = "disabled";
 			};

-			iomuxc: iomuxc@43fac000 {
+			iomuxc: pinmux@43fac000 {
 				compatible = "fsl,imx25-iomuxc";
 				reg = <0x43fac000 0x4000>;
 			};
@@ -305,7 +305,7 @@
 					status = "disabled";
 				};

-				tsc: tcq@50030400 {
+				tsc: touchscreen@50030400 {
 					compatible = "fsl,imx25-tcq";
 					reg = <0x50030400 0x60>;
 					interrupt-parent = <&tscadc>;
--- a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
@@ -24,36 +24,34 @@
 };

 &iomuxc {
-	imx27-apf27 {
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-			>;
-		};
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
@@ -122,116 +122,114 @@
 };

 &iomuxc {
-	imx27-apf27dev {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
-				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
-				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+			MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+			MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+		>;
+	};

-		pinctrl_cspi1_cs: cspi1csgrp {
-			fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
-		};
+	pinctrl_cspi1_cs: cspi1csgrp {
+		fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
+	};

-		pinctrl_cspi2: cspi2grp {
-			fsl,pins = <
-				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
-				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
-				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
-			>;
-		};
+	pinctrl_cspi2: cspi2grp {
+		fsl,pins = <
+			MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+			MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+			MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+		>;
+	};

-		pinctrl_cspi2_cs: cspi2csgrp {
-			fsl,pins = <
-				MX27_PAD_CSI_D5__GPIO2_17 0x0
-				MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
-				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
-			>;
-		};
+	pinctrl_cspi2_cs: cspi2csgrp {
+		fsl,pins = <
+			MX27_PAD_CSI_D5__GPIO2_17 0x0
+			MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
+			MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
+		>;
+	};

-		pinctrl_gpio_leds: gpioledsgrp {
-			fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
-		};
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
+	};

-		pinctrl_gpio_keys: gpiokeysgrp {
-			fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
-		};
+	pinctrl_gpio_keys: gpiokeysgrp {
+		fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
+	};

-		pinctrl_imxfb1: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_CLS__CLS 0x0
-				MX27_PAD_CONTRAST__CONTRAST 0x0
-				MX27_PAD_LD0__LD0 0x0
-				MX27_PAD_LD1__LD1 0x0
-				MX27_PAD_LD2__LD2 0x0
-				MX27_PAD_LD3__LD3 0x0
-				MX27_PAD_LD4__LD4 0x0
-				MX27_PAD_LD5__LD5 0x0
-				MX27_PAD_LD6__LD6 0x0
-				MX27_PAD_LD7__LD7 0x0
-				MX27_PAD_LD8__LD8 0x0
-				MX27_PAD_LD9__LD9 0x0
-				MX27_PAD_LD10__LD10 0x0
-				MX27_PAD_LD11__LD11 0x0
-				MX27_PAD_LD12__LD12 0x0
-				MX27_PAD_LD13__LD13 0x0
-				MX27_PAD_LD14__LD14 0x0
-				MX27_PAD_LD15__LD15 0x0
-				MX27_PAD_LD16__LD16 0x0
-				MX27_PAD_LD17__LD17 0x0
-				MX27_PAD_LSCLK__LSCLK 0x0
-				MX27_PAD_OE_ACD__OE_ACD 0x0
-				MX27_PAD_PS__PS 0x0
-				MX27_PAD_REV__REV 0x0
-				MX27_PAD_SPL_SPR__SPL_SPR 0x0
-				MX27_PAD_HSYNC__HSYNC 0x0
-				MX27_PAD_VSYNC__VSYNC 0x0
-			>;
-		};
+	pinctrl_imxfb1: imxfbgrp {
+		fsl,pins = <
+			MX27_PAD_CLS__CLS 0x0
+			MX27_PAD_CONTRAST__CONTRAST 0x0
+			MX27_PAD_LD0__LD0 0x0
+			MX27_PAD_LD1__LD1 0x0
+			MX27_PAD_LD2__LD2 0x0
+			MX27_PAD_LD3__LD3 0x0
+			MX27_PAD_LD4__LD4 0x0
+			MX27_PAD_LD5__LD5 0x0
+			MX27_PAD_LD6__LD6 0x0
+			MX27_PAD_LD7__LD7 0x0
+			MX27_PAD_LD8__LD8 0x0
+			MX27_PAD_LD9__LD9 0x0
+			MX27_PAD_LD10__LD10 0x0
+			MX27_PAD_LD11__LD11 0x0
+			MX27_PAD_LD12__LD12 0x0
+			MX27_PAD_LD13__LD13 0x0
+			MX27_PAD_LD14__LD14 0x0
+			MX27_PAD_LD15__LD15 0x0
+			MX27_PAD_LD16__LD16 0x0
+			MX27_PAD_LD17__LD17 0x0
+			MX27_PAD_LSCLK__LSCLK 0x0
+			MX27_PAD_OE_ACD__OE_ACD 0x0
+			MX27_PAD_PS__PS 0x0
+			MX27_PAD_REV__REV 0x0
+			MX27_PAD_SPL_SPR__SPL_SPR 0x0
+			MX27_PAD_HSYNC__HSYNC 0x0
+			MX27_PAD_VSYNC__VSYNC 0x0
+		>;
+	};

-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA 0x0
-				MX27_PAD_I2C_CLK__I2C_CLK 0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA 0x0
+			MX27_PAD_I2C_CLK__I2C_CLK 0x0
+		>;
+	};

-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+			MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+		>;
+	};

-		pinctrl_max1027: max1027 {
-			 fsl,pins = <
-				 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
-				 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
-			>;
-		};
+	pinctrl_max1027: max1027grp {
+		 fsl,pins = <
+			 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
+			 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
+		>;
+	};

-		pinctrl_pwm: pwmgrp {
-			fsl,pins = <
-				MX27_PAD_PWMO__PWMO 0x0
-			>;
-		};
+	pinctrl_pwm: pwmgrp {
+		fsl,pins = <
+			MX27_PAD_PWMO__PWMO 0x0
+		>;
+	};

-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK 0x0
+			MX27_PAD_SD2_CMD__SD2_CMD 0x0
+			MX27_PAD_SD2_D0__SD2_D0 0x0
+			MX27_PAD_SD2_D1__SD2_D1 0x0
+			MX27_PAD_SD2_D2__SD2_D2 0x0
+			MX27_PAD_SD2_D3__SD2_D3 0x0
+		>;
+	};

-		pinctrl_sdhc2_cd: sdhc2cdgrp {
-			fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
-		};
+	pinctrl_sdhc2_cd: sdhc2cdgrp {
+		fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
@@ -100,52 +100,52 @@
 		fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
 	};

-	uart8250@3,200000 {
+	serial@3,200000 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_uart8250_1>;
 		compatible = "ns8250";
 		clocks = <&clk14745600>;
 		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
-		interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
+		interrupts-extended = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
 		reg = <3 0x200000 0x1000>;
 		reg-shift = <1>;
 		reg-io-width = <1>;
 		no-loopback-test;
 	};

-	uart8250@3,400000 {
+	serial@3,400000 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_uart8250_2>;
 		compatible = "ns8250";
 		clocks = <&clk14745600>;
 		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
-		interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
+		interrupts-extended = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
 		reg = <3 0x400000 0x1000>;
 		reg-shift = <1>;
 		reg-io-width = <1>;
 		no-loopback-test;
 	};

-	uart8250@3,800000 {
+	serial@3,800000 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_uart8250_3>;
 		compatible = "ns8250";
 		clocks = <&clk14745600>;
 		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
-		interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
+		interrupts-extended = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
 		reg = <3 0x800000 0x1000>;
 		reg-shift = <1>;
 		reg-io-width = <1>;
 		no-loopback-test;
 	};

-	uart8250@3,1000000 {
+	serial@3,1000000 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_uart8250_4>;
 		compatible = "ns8250";
 		clocks = <&clk14745600>;
 		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
-		interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
+		interrupts-extended = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
 		reg = <3 0x1000000 0x1000>;
 		reg-shift = <1>;
 		reg-io-width = <1>;
@@ -154,131 +154,129 @@
 };

 &iomuxc {
-	imx27-eukrea-cpuimx27 {
-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0		0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1		0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2		0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3		0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER		0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1		0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2		0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3		0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO		0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC		0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS		0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK		0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0		0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV		0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK		0x0
-				MX27_PAD_ATA_DATA13__FEC_COL		0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER		0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN		0x0
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0		0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1		0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2		0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3		0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER		0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1		0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2		0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3		0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO		0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC		0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS		0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK		0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0		0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV		0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK		0x0
+			MX27_PAD_ATA_DATA13__FEC_COL		0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER		0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN		0x0
+		>;
+	};

-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA		0x0
-				MX27_PAD_I2C_CLK__I2C_CLK		0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA		0x0
+			MX27_PAD_I2C_CLK__I2C_CLK		0x0
+		>;
+	};

-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB			0x0
-				MX27_PAD_NFCLE__NFCLE			0x0
-				MX27_PAD_NFWP_B__NFWP_B			0x0
-				MX27_PAD_NFCE_B__NFCE_B			0x0
-				MX27_PAD_NFALE__NFALE			0x0
-				MX27_PAD_NFRE_B__NFRE_B			0x0
-				MX27_PAD_NFWE_B__NFWE_B			0x0
-			>;
-		};
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB			0x0
+			MX27_PAD_NFCLE__NFCLE			0x0
+			MX27_PAD_NFWP_B__NFWP_B			0x0
+			MX27_PAD_NFCE_B__NFCE_B			0x0
+			MX27_PAD_NFALE__NFALE			0x0
+			MX27_PAD_NFRE_B__NFRE_B			0x0
+			MX27_PAD_NFWE_B__NFWE_B			0x0
+		>;
+	};

-		pinctrl_owire: owiregrp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE			0x0
-			>;
-		};
+	pinctrl_owire: owiregrp {
+		fsl,pins = <
+			MX27_PAD_RTCK__OWIRE			0x0
+		>;
+	};

-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK		0x0
-				MX27_PAD_SD2_CMD__SD2_CMD		0x0
-				MX27_PAD_SD2_D0__SD2_D0			0x0
-				MX27_PAD_SD2_D1__SD2_D1			0x0
-				MX27_PAD_SD2_D2__SD2_D2			0x0
-				MX27_PAD_SD2_D3__SD2_D3			0x0
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK		0x0
+			MX27_PAD_SD2_CMD__SD2_CMD		0x0
+			MX27_PAD_SD2_D0__SD2_D0			0x0
+			MX27_PAD_SD2_D1__SD2_D1			0x0
+			MX27_PAD_SD2_D2__SD2_D2			0x0
+			MX27_PAD_SD2_D3__SD2_D3			0x0
+		>;
+	};

-		pinctrl_uart4: uart4grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_TXDM__UART4_TXD		0x0
-				MX27_PAD_USBH1_RXDP__UART4_RXD		0x0
-				MX27_PAD_USBH1_TXDP__UART4_CTS		0x0
-				MX27_PAD_USBH1_FS__UART4_RTS		0x0
-			>;
-		};
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_TXDM__UART4_TXD		0x0
+			MX27_PAD_USBH1_RXDP__UART4_RXD		0x0
+			MX27_PAD_USBH1_TXDP__UART4_CTS		0x0
+			MX27_PAD_USBH1_FS__UART4_RTS		0x0
+		>;
+	};

-		pinctrl_uart8250_1: uart82501grp {
-			fsl,pins = <
-				MX27_PAD_USB_PWR__GPIO2_23		0x0
-			>;
-		};
+	pinctrl_uart8250_1: uart82501grp {
+		fsl,pins = <
+			MX27_PAD_USB_PWR__GPIO2_23		0x0
+		>;
+	};

-		pinctrl_uart8250_2: uart82502grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0
-			>;
-		};
+	pinctrl_uart8250_2: uart82502grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_SUSP__GPIO2_22		0x0
+		>;
+	};

-		pinctrl_uart8250_3: uart82503grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_OE_B__GPIO2_27		0x0
-			>;
-		};
+	pinctrl_uart8250_3: uart82503grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_OE_B__GPIO2_27		0x0
+		>;
+	};

-		pinctrl_uart8250_4: uart82504grp {
-			fsl,pins = <
-				MX27_PAD_USBH1_RXDM__GPIO2_30		0x0
-			>;
-		};
+	pinctrl_uart8250_4: uart82504grp {
+		fsl,pins = <
+			MX27_PAD_USBH1_RXDM__GPIO2_30		0x0
+		>;
+	};

-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
-				MX27_PAD_USBH2_STP__USBH2_STP		0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
-			>;
-		};
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
+			MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
+			MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
+			MX27_PAD_USBH2_STP__USBH2_STP		0x0
+			MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
+			MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
+			MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
+			MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
+			MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
+			MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
+			MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
+			MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
+		>;
+	};

-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
+		>;
 	};
 };
--- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -76,7 +76,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_touch>;
 		reg = <0>;
-		interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
+		interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
 		spi-cpol;
 		spi-max-frequency = <1500000>;
 		ti,keep-vref-on;
@@ -147,113 +147,111 @@
 };

 &iomuxc {
-	imx27-eukrea-cpuimx27-baseboard {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_MISO__CSPI1_MISO	0x0
-				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI	0x0
-				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK	0x0
-				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* CS0 */
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_MISO__CSPI1_MISO	0x0
+			MX27_PAD_CSPI1_MOSI__CSPI1_MOSI	0x0
+			MX27_PAD_CSPI1_SCLK__CSPI1_SCLK	0x0
+			MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* CS0 */
+		>;
+	};

-		pinctrl_backlight: backlightgrp {
-			fsl,pins = <
-				MX27_PAD_PWMO__GPIO5_5		0x0
-			>;
-		};
+	pinctrl_backlight: backlightgrp {
+		fsl,pins = <
+			MX27_PAD_PWMO__GPIO5_5		0x0
+		>;
+	};

-		pinctrl_gpioleds: gpioledsgrp {
-			fsl,pins = <
-				MX27_PAD_PC_PWRON__GPIO6_16	0x0
-				MX27_PAD_PC_CD2_B__GPIO6_19	0x0
-			>;
-		};
+	pinctrl_gpioleds: gpioledsgrp {
+		fsl,pins = <
+			MX27_PAD_PC_PWRON__GPIO6_16	0x0
+			MX27_PAD_PC_CD2_B__GPIO6_19	0x0
+		>;
+	};

-		pinctrl_imxfb: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_LD0__LD0		0x0
-				MX27_PAD_LD1__LD1		0x0
-				MX27_PAD_LD2__LD2		0x0
-				MX27_PAD_LD3__LD3		0x0
-				MX27_PAD_LD4__LD4		0x0
-				MX27_PAD_LD5__LD5		0x0
-				MX27_PAD_LD6__LD6		0x0
-				MX27_PAD_LD7__LD7		0x0
-				MX27_PAD_LD8__LD8		0x0
-				MX27_PAD_LD9__LD9		0x0
-				MX27_PAD_LD10__LD10		0x0
-				MX27_PAD_LD11__LD11		0x0
-				MX27_PAD_LD12__LD12		0x0
-				MX27_PAD_LD13__LD13		0x0
-				MX27_PAD_LD14__LD14		0x0
-				MX27_PAD_LD15__LD15		0x0
-				MX27_PAD_LD16__LD16		0x0
-				MX27_PAD_LD17__LD17		0x0
-				MX27_PAD_CONTRAST__CONTRAST	0x0
-				MX27_PAD_OE_ACD__OE_ACD		0x0
-				MX27_PAD_HSYNC__HSYNC		0x0
-				MX27_PAD_VSYNC__VSYNC		0x0
-			>;
-		};
+	pinctrl_imxfb: imxfbgrp {
+		fsl,pins = <
+			MX27_PAD_LD0__LD0		0x0
+			MX27_PAD_LD1__LD1		0x0
+			MX27_PAD_LD2__LD2		0x0
+			MX27_PAD_LD3__LD3		0x0
+			MX27_PAD_LD4__LD4		0x0
+			MX27_PAD_LD5__LD5		0x0
+			MX27_PAD_LD6__LD6		0x0
+			MX27_PAD_LD7__LD7		0x0
+			MX27_PAD_LD8__LD8		0x0
+			MX27_PAD_LD9__LD9		0x0
+			MX27_PAD_LD10__LD10		0x0
+			MX27_PAD_LD11__LD11		0x0
+			MX27_PAD_LD12__LD12		0x0
+			MX27_PAD_LD13__LD13		0x0
+			MX27_PAD_LD14__LD14		0x0
+			MX27_PAD_LD15__LD15		0x0
+			MX27_PAD_LD16__LD16		0x0
+			MX27_PAD_LD17__LD17		0x0
+			MX27_PAD_CONTRAST__CONTRAST	0x0
+			MX27_PAD_OE_ACD__OE_ACD		0x0
+			MX27_PAD_HSYNC__HSYNC		0x0
+			MX27_PAD_VSYNC__VSYNC		0x0
+		>;
+	};

-		pinctrl_lcdreg: lcdreggrp {
-			fsl,pins = <
-				MX27_PAD_CLS__GPIO1_25		0x0
-			>;
-		};
+	pinctrl_lcdreg: lcdreggrp {
+		fsl,pins = <
+			MX27_PAD_CLS__GPIO1_25		0x0
+		>;
+	};

-		pinctrl_sdhc1: sdhc1grp {
-			fsl,pins = <
-				MX27_PAD_SD1_CLK__SD1_CLK	0x0
-				MX27_PAD_SD1_CMD__SD1_CMD	0x0
-				MX27_PAD_SD1_D0__SD1_D0		0x0
-				MX27_PAD_SD1_D1__SD1_D1		0x0
-				MX27_PAD_SD1_D2__SD1_D2		0x0
-				MX27_PAD_SD1_D3__SD1_D3		0x0
-			>;
-		};
+	pinctrl_sdhc1: sdhc1grp {
+		fsl,pins = <
+			MX27_PAD_SD1_CLK__SD1_CLK	0x0
+			MX27_PAD_SD1_CMD__SD1_CMD	0x0
+			MX27_PAD_SD1_D0__SD1_D0		0x0
+			MX27_PAD_SD1_D1__SD1_D1		0x0
+			MX27_PAD_SD1_D2__SD1_D2		0x0
+			MX27_PAD_SD1_D3__SD1_D3		0x0
+		>;
+	};

-		pinctrl_ssi1: ssi1grp {
-			fsl,pins = <
-				MX27_PAD_SSI4_CLK__SSI4_CLK	0x0
-				MX27_PAD_SSI4_FS__SSI4_FS	0x0
-				MX27_PAD_SSI4_RXDAT__SSI4_RXDAT	0x1
-				MX27_PAD_SSI4_TXDAT__SSI4_TXDAT	0x1
-			>;
-		};
+	pinctrl_ssi1: ssi1grp {
+		fsl,pins = <
+			MX27_PAD_SSI4_CLK__SSI4_CLK	0x0
+			MX27_PAD_SSI4_FS__SSI4_FS	0x0
+			MX27_PAD_SSI4_RXDAT__SSI4_RXDAT	0x1
+			MX27_PAD_SSI4_TXDAT__SSI4_TXDAT	0x1
+		>;
+	};

-		pinctrl_touch: touchgrp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_RDY__GPIO4_25	0x0 /* IRQ */
-			>;
-		};
+	pinctrl_touch: touchgrp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_RDY__GPIO4_25	0x0 /* IRQ */
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD	0x0
-				MX27_PAD_UART1_RXD__UART1_RXD	0x0
-				MX27_PAD_UART1_CTS__UART1_CTS	0x0
-				MX27_PAD_UART1_RTS__UART1_RTS	0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD	0x0
+			MX27_PAD_UART1_RXD__UART1_RXD	0x0
+			MX27_PAD_UART1_CTS__UART1_CTS	0x0
+			MX27_PAD_UART1_RTS__UART1_RTS	0x0
+		>;
+	};

-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD	0x0
-				MX27_PAD_UART2_RXD__UART2_RXD	0x0
-				MX27_PAD_UART2_CTS__UART2_CTS	0x0
-				MX27_PAD_UART2_RTS__UART2_RTS	0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX27_PAD_UART2_TXD__UART2_TXD	0x0
+			MX27_PAD_UART2_RXD__UART2_RXD	0x0
+			MX27_PAD_UART2_CTS__UART2_CTS	0x0
+			MX27_PAD_UART2_RTS__UART2_RTS	0x0
+		>;
+	};

-		pinctrl_uart3: uart3grp {
-			fsl,pins = <
-				MX27_PAD_UART3_TXD__UART3_TXD	0x0
-				MX27_PAD_UART3_RXD__UART3_RXD	0x0
-				MX27_PAD_UART3_CTS__UART3_CTS	0x0
-				MX27_PAD_UART3_RTS__UART3_RTS	0x0
-			>;
-		};
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX27_PAD_UART3_TXD__UART3_TXD	0x0
+			MX27_PAD_UART3_RXD__UART3_RXD	0x0
+			MX27_PAD_UART3_CTS__UART3_CTS	0x0
+			MX27_PAD_UART3_RTS__UART3_RTS	0x0
+		>;
 	};
 };
--- a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
@@ -110,76 +110,74 @@
 };

 &iomuxc {
-	imx27-pdk {
-		pinctrl_cspi2: cspi2grp {
-			fsl,pins = <
-				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
-				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
-				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
-				MX27_PAD_CSPI2_SS0__GPIO4_21	0x0 /* SPI2 CS0 */
-				MX27_PAD_TOUT__GPIO3_14		0x0 /* PMIC IRQ */
-			>;
-		};
+	pinctrl_cspi2: cspi2grp {
+		fsl,pins = <
+			MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+			MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+			MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+			MX27_PAD_CSPI2_SS0__GPIO4_21	0x0 /* SPI2 CS0 */
+			MX27_PAD_TOUT__GPIO3_14		0x0 /* PMIC IRQ */
+		>;
+	};

-		pinctrl_fec: fecgrp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-			>;
-		};
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+		>;
+	};

-		pinctrl_nand: nandgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB	0x0
-				MX27_PAD_NFCLE__NFCLE	0x0
-				MX27_PAD_NFWP_B__NFWP_B	0x0
-				MX27_PAD_NFCE_B__NFCE_B	0x0
-				MX27_PAD_NFALE__NFALE	0x0
-				MX27_PAD_NFRE_B__NFRE_B	0x0
-				MX27_PAD_NFWE_B__NFWE_B	0x0
-			>;
-		};
+	pinctrl_nand: nandgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB	0x0
+			MX27_PAD_NFCLE__NFCLE	0x0
+			MX27_PAD_NFWP_B__NFWP_B	0x0
+			MX27_PAD_NFCE_B__NFCE_B	0x0
+			MX27_PAD_NFALE__NFALE	0x0
+			MX27_PAD_NFRE_B__NFRE_B	0x0
+			MX27_PAD_NFWE_B__NFWE_B	0x0
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+			MX27_PAD_UART1_CTS__UART1_CTS 0x0
+			MX27_PAD_UART1_RTS__UART1_RTS 0x0
+		>;
+	};

-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+		>;
 	};
 };
--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
@@ -65,58 +65,56 @@
 };

 &iomuxc {
-	imx27-phycard-s-rdk {
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA 0x0
-				MX27_PAD_I2C_CLK__I2C_CLK 0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA 0x0
+			MX27_PAD_I2C_CLK__I2C_CLK 0x0
+		>;
+	};

-		pinctrl_owire1: owire1grp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE 0x0
-			>;
-		};
+	pinctrl_owire1: owire1grp {
+		fsl,pins = <
+			MX27_PAD_RTCK__OWIRE 0x0
+		>;
+	};

-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-				MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK 0x0
+			MX27_PAD_SD2_CMD__SD2_CMD 0x0
+			MX27_PAD_SD2_D0__SD2_D0 0x0
+			MX27_PAD_SD2_D1__SD2_D1 0x0
+			MX27_PAD_SD2_D2__SD2_D2 0x0
+			MX27_PAD_SD2_D3__SD2_D3 0x0
+			MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+			MX27_PAD_UART1_CTS__UART1_CTS 0x0
+			MX27_PAD_UART1_RTS__UART1_RTS 0x0
+		>;
+	};

-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD 0x0
-				MX27_PAD_UART2_RXD__UART2_RXD 0x0
-				MX27_PAD_UART2_CTS__UART2_CTS 0x0
-				MX27_PAD_UART2_RTS__UART2_RTS 0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX27_PAD_UART2_TXD__UART2_TXD 0x0
+			MX27_PAD_UART2_RXD__UART2_RXD 0x0
+			MX27_PAD_UART2_CTS__UART2_CTS 0x0
+			MX27_PAD_UART2_RTS__UART2_RTS 0x0
+		>;
+	};

-		pinctrl_uart3: uart3grp {
-			fsl,pins = <
-				MX27_PAD_UART3_TXD__UART3_TXD 0x0
-				MX27_PAD_UART3_RXD__UART3_RXD 0x0
-				MX27_PAD_UART3_CTS__UART3_CTS 0x0
-				MX27_PAD_UART3_RTS__UART3_RTS 0x0
-			>;
-		};
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX27_PAD_UART3_TXD__UART3_TXD 0x0
+			MX27_PAD_UART3_RXD__UART3_RXD 0x0
+			MX27_PAD_UART3_CTS__UART3_CTS 0x0
+			MX27_PAD_UART3_RTS__UART3_RTS 0x0
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
@@ -58,94 +58,92 @@
 };

 &iomuxc {
-	imx27-phycard-s-som {
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-			>;
-		};
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+		>;
+	};

-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+			MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+		>;
+	};

-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB 0x0
-				MX27_PAD_NFCLE__NFCLE 0x0
-				MX27_PAD_NFWP_B__NFWP_B 0x0
-				MX27_PAD_NFCE_B__NFCE_B 0x0
-				MX27_PAD_NFALE__NFALE 0x0
-				MX27_PAD_NFRE_B__NFRE_B 0x0
-				MX27_PAD_NFWE_B__NFWE_B 0x0
-			>;
-		};
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB 0x0
+			MX27_PAD_NFCLE__NFCLE 0x0
+			MX27_PAD_NFWP_B__NFWP_B 0x0
+			MX27_PAD_NFCE_B__NFCE_B 0x0
+			MX27_PAD_NFALE__NFALE 0x0
+			MX27_PAD_NFRE_B__NFRE_B 0x0
+			MX27_PAD_NFWE_B__NFWE_B 0x0
+		>;
+	};

-		pinctrl_usbotgphy: usbotgphygrp {
-			fsl,pins = <
-				MX27_PAD_USBH1_RCV__GPIO2_25		0x1 /* reset gpio */
-			>;
-		};
+	pinctrl_usbotgphy: usbotgphygrp {
+		fsl,pins = <
+			MX27_PAD_USBH1_RCV__GPIO2_25		0x1 /* reset gpio */
+		>;
+	};

-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
+		>;
+	};

-		pinctrl_usbh2phy: usbh2phygrp {
-			fsl,pins = <
-				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0 /* reset gpio */
-			>;
-		};
+	pinctrl_usbh2phy: usbh2phygrp {
+		fsl,pins = <
+			MX27_PAD_USBH1_SUSP__GPIO2_22		0x0 /* reset gpio */
+		>;
+	};

-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
-				MX27_PAD_USBH2_STP__USBH2_STP		0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
-			>;
-		};
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
+			MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
+			MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
+			MX27_PAD_USBH2_STP__USBH2_STP		0x0
+			MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
+			MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
+			MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
+			MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
+			MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
+			MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
+			MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
+			MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
@@ -89,119 +89,117 @@
 };

 &iomuxc {
-	imx27_phycore_rdk {
-		pinctrl_csien: csiengrp {
-			fsl,pins = <
-				MX27_PAD_USB_OC_B__GPIO2_24 0x0
-			>;
-		};
+	pinctrl_csien: csiengrp {
+		fsl,pins = <
+			MX27_PAD_USB_OC_B__GPIO2_24 0x0
+		>;
+	};

-		pinctrl_cspi1cs1: cspi1cs1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
-			>;
-		};
+	pinctrl_cspi1cs1: cspi1cs1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
+		>;
+	};

-		pinctrl_imxfb1: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_LD0__LD0 0x0
-				MX27_PAD_LD1__LD1 0x0
-				MX27_PAD_LD2__LD2 0x0
-				MX27_PAD_LD3__LD3 0x0
-				MX27_PAD_LD4__LD4 0x0
-				MX27_PAD_LD5__LD5 0x0
-				MX27_PAD_LD6__LD6 0x0
-				MX27_PAD_LD7__LD7 0x0
-				MX27_PAD_LD8__LD8 0x0
-				MX27_PAD_LD9__LD9 0x0
-				MX27_PAD_LD10__LD10 0x0
-				MX27_PAD_LD11__LD11 0x0
-				MX27_PAD_LD12__LD12 0x0
-				MX27_PAD_LD13__LD13 0x0
-				MX27_PAD_LD14__LD14 0x0
-				MX27_PAD_LD15__LD15 0x0
-				MX27_PAD_LD16__LD16 0x0
-				MX27_PAD_LD17__LD17 0x0
-				MX27_PAD_CLS__CLS 0x0
-				MX27_PAD_CONTRAST__CONTRAST 0x0
-				MX27_PAD_LSCLK__LSCLK 0x0
-				MX27_PAD_OE_ACD__OE_ACD 0x0
-				MX27_PAD_PS__PS 0x0
-				MX27_PAD_REV__REV 0x0
-				MX27_PAD_SPL_SPR__SPL_SPR 0x0
-				MX27_PAD_HSYNC__HSYNC 0x0
-				MX27_PAD_VSYNC__VSYNC 0x0
-			>;
-		};
+	pinctrl_imxfb1: imxfbgrp {
+		fsl,pins = <
+			MX27_PAD_LD0__LD0 0x0
+			MX27_PAD_LD1__LD1 0x0
+			MX27_PAD_LD2__LD2 0x0
+			MX27_PAD_LD3__LD3 0x0
+			MX27_PAD_LD4__LD4 0x0
+			MX27_PAD_LD5__LD5 0x0
+			MX27_PAD_LD6__LD6 0x0
+			MX27_PAD_LD7__LD7 0x0
+			MX27_PAD_LD8__LD8 0x0
+			MX27_PAD_LD9__LD9 0x0
+			MX27_PAD_LD10__LD10 0x0
+			MX27_PAD_LD11__LD11 0x0
+			MX27_PAD_LD12__LD12 0x0
+			MX27_PAD_LD13__LD13 0x0
+			MX27_PAD_LD14__LD14 0x0
+			MX27_PAD_LD15__LD15 0x0
+			MX27_PAD_LD16__LD16 0x0
+			MX27_PAD_LD17__LD17 0x0
+			MX27_PAD_CLS__CLS 0x0
+			MX27_PAD_CONTRAST__CONTRAST 0x0
+			MX27_PAD_LSCLK__LSCLK 0x0
+			MX27_PAD_OE_ACD__OE_ACD 0x0
+			MX27_PAD_PS__PS 0x0
+			MX27_PAD_REV__REV 0x0
+			MX27_PAD_SPL_SPR__SPL_SPR 0x0
+			MX27_PAD_HSYNC__HSYNC 0x0
+			MX27_PAD_VSYNC__VSYNC 0x0
+		>;
+	};

-		pinctrl_i2c1: i2c1grp {
-			/* Add pullup to DATA line */
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA	0x1
-				MX27_PAD_I2C_CLK__I2C_CLK	0x0
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		/* Add pullup to DATA line */
+		fsl,pins = <
+			MX27_PAD_I2C_DATA__I2C_DATA	0x1
+			MX27_PAD_I2C_CLK__I2C_CLK	0x0
+		>;
+	};

-		pinctrl_owire1: owire1grp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE 0x0
-			>;
-		};
+	pinctrl_owire1: owire1grp {
+		fsl,pins = <
+			MX27_PAD_RTCK__OWIRE 0x0
+		>;
+	};

-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-				MX27_PAD_SSI3_FS__GPIO3_28	0x0 /* WP */
-				MX27_PAD_SSI3_RXDAT__GPIO3_29	0x0 /* CD */
-			>;
-		};
+	pinctrl_sdhc2: sdhc2grp {
+		fsl,pins = <
+			MX27_PAD_SD2_CLK__SD2_CLK 0x0
+			MX27_PAD_SD2_CMD__SD2_CMD 0x0
+			MX27_PAD_SD2_D0__SD2_D0 0x0
+			MX27_PAD_SD2_D1__SD2_D1 0x0
+			MX27_PAD_SD2_D2__SD2_D2 0x0
+			MX27_PAD_SD2_D3__SD2_D3 0x0
+			MX27_PAD_SSI3_FS__GPIO3_28	0x0 /* WP */
+			MX27_PAD_SSI3_RXDAT__GPIO3_29	0x0 /* CD */
+		>;
+	};

-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX27_PAD_UART1_TXD__UART1_TXD 0x0
+			MX27_PAD_UART1_RXD__UART1_RXD 0x0
+			MX27_PAD_UART1_CTS__UART1_CTS 0x0
+			MX27_PAD_UART1_RTS__UART1_RTS 0x0
+		>;
+	};

-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD 0x0
-				MX27_PAD_UART2_RXD__UART2_RXD 0x0
-				MX27_PAD_UART2_CTS__UART2_CTS 0x0
-				MX27_PAD_UART2_RTS__UART2_RTS 0x0
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX27_PAD_UART2_TXD__UART2_TXD 0x0
+			MX27_PAD_UART2_RXD__UART2_RXD 0x0
+			MX27_PAD_UART2_CTS__UART2_CTS 0x0
+			MX27_PAD_UART2_RTS__UART2_RTS 0x0
+		>;
+	};

-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
-				MX27_PAD_USBH2_STP__USBH2_STP 0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
-			>;
-		};
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
+			MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
+			MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
+			MX27_PAD_USBH2_STP__USBH2_STP 0x0
+			MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
+			MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
+			MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
+			MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
+			MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
+			MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
+			MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
+			MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
+		>;
+	};

-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX27_PAD_CS4_B__CS4_B		0x0 /* CS4 */
-				MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
-			>;
-		};
+	pinctrl_weim: weimgrp {
+		fsl,pins = <
+			MX27_PAD_CS4_B__CS4_B		0x0 /* CS4 */
+			MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
@@ -192,90 +192,88 @@
 };

 &iomuxc {
-	imx27_phycore_som {
-		pinctrl_cspi1: cspi1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
-				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
-				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
-				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
-			>;
-		};
+	pinctrl_cspi1: cspi1grp {
+		fsl,pins = <
+			MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+			MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+			MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+			MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
+		>;
+	};

-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-				MX27_PAD_ATA_DATA13__FEC_COL 0x0
-				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-				MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
-			>;
-		};
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+			MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+			MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+			MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+			MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+			MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+			MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+			MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+			MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+			MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+			MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+			MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+			MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+			MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+			MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+			MX27_PAD_ATA_DATA13__FEC_COL 0x0
+			MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+			MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+			MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
+		>;
+	};

-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+			MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+		>;
+	};

-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <
-				MX27_PAD_NFRB__NFRB 0x0
-				MX27_PAD_NFCLE__NFCLE 0x0
-				MX27_PAD_NFWP_B__NFWP_B 0x0
-				MX27_PAD_NFCE_B__NFCE_B 0x0
-				MX27_PAD_NFALE__NFALE 0x0
-				MX27_PAD_NFRE_B__NFRE_B 0x0
-				MX27_PAD_NFWE_B__NFWE_B 0x0
-			>;
-		};
+	pinctrl_nfc: nfcgrp {
+		fsl,pins = <
+			MX27_PAD_NFRB__NFRB 0x0
+			MX27_PAD_NFCLE__NFCLE 0x0
+			MX27_PAD_NFWP_B__NFWP_B 0x0
+			MX27_PAD_NFCE_B__NFCE_B 0x0
+			MX27_PAD_NFALE__NFALE 0x0
+			MX27_PAD_NFRE_B__NFRE_B 0x0
+			MX27_PAD_NFWE_B__NFWE_B 0x0
+		>;
+	};

-		pinctrl_pmic: pmicgrp {
-			fsl,pins = <
-				MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
-			>;
-		};
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
+		>;
+	};

-		pinctrl_ssi1: ssi1grp {
-			fsl,pins = <
-				MX27_PAD_SSI1_FS__SSI1_FS 0x0
-				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
-				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
-				MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
-			>;
-		};
+	pinctrl_ssi1: ssi1grp {
+		fsl,pins = <
+			MX27_PAD_SSI1_FS__SSI1_FS 0x0
+			MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
+			MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
+			MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
+		>;
+	};

-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
-				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
-				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
-				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
-				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
-				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
-				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
-				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
-				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
-				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
-				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
-				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+			MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+			MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+			MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+			MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+			MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+			MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+			MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+			MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+			MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+			MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+		>;
 	};
 };

--- a/arch/arm/boot/dts/nxp/imx/imx27.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx27.dtsi
@@ -49,7 +49,7 @@

 	clocks {
 		clk_osc26m: osc26m {
-			compatible = "fsl,imx-osc26m", "fixed-clock";
+			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <26000000>;
 		};
@@ -289,7 +289,7 @@
 				status = "disabled";
 			};

-			iomuxc: iomuxc@10015000 {
+			iomuxc: pinmux@10015000 {
 				compatible = "fsl,imx27-iomuxc";
 				reg = <0x10015000 0x600>;
 				#address-cells = <1>;
--- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi
@@ -333,7 +333,7 @@
 			};
 		};

-		emi@b8000000 { /* External Memory Interface */
+		emi-bus@b8000000 { /* External Memory Interface */
 			compatible = "simple-bus";
 			reg = <0xb8000000 0x5000>;
 			ranges;
--- a/arch/arm/boot/dts/nxp/imx/imx35.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi
@@ -79,7 +79,7 @@
 				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
 				reg = <0x43f80000 0x4000>;
 				clocks = <&clks 51>;
-				clock-names = "ipg_per";
+				clock-names = "ipg";
 				interrupts = <10>;
 				status = "disabled";
 			};
@@ -90,7 +90,7 @@
 				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
 				reg = <0x43f84000 0x4000>;
 				clocks = <&clks 53>;
-				clock-names = "ipg_per";
+				clock-names = "ipg";
 				interrupts = <3>;
 				status = "disabled";
 			};
@@ -119,7 +119,7 @@
 				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
 				reg = <0x43f98000 0x4000>;
 				clocks = <&clks 52>;
-				clock-names = "ipg_per";
+				clock-names = "ipg";
 				interrupts = <4>;
 				status = "disabled";
 			};
@@ -356,7 +356,7 @@
 			};
 		};

-		emi@80000000 { /* External Memory Interface */
+		emi-bus@80000000 { /* External Memory Interface */
 			compatible = "fsl,emi", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -393,21 +393,13 @@
 		};
 	};

-	usbphy {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
+	usbphy0: usb-phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};

-		usbphy0: usb-phy@0 {
-			reg = <0>;
-			compatible = "usb-nop-xceiv";
-			#phy-cells = <0>;
-		};
-
-		usbphy1: usb-phy@1 {
-			reg = <1>;
-			compatible = "usb-nop-xceiv";
-			#phy-cells = <0>;
-		};
+	usbphy1: usb-phy1 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
--- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts
@@ -327,7 +327,7 @@
 		};
 	};

-	flash: at45db321d@1 {
+	flash: flash@1 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
--- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts
@@ -141,7 +141,7 @@
 	pinctrl-0 = <&pinctrl_weim>;
 	status = "okay";

-	fpga@0 {
+	fpga-bus@0,0 {
 		compatible = "simple-bus";
 		fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
 				      0x00000000 0x1c092480 0x00000000>;
--- a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts
@@ -31,6 +31,20 @@
 			linux,code = <KEY_VOLUMEDOWN>;
 		};
 	};
+
+	reg_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 };

 &esdhc1 {
@@ -253,6 +267,10 @@
 	codec: sgtl5000@a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
+		#sound-dai-cells = <0>;
+		clocks = <&clks IMX5_CLK_DUMMY>;
+		VDDA-supply = <&reg_1v8>;
+		VDDIO-supply = <&reg_3v3>;
 	};

 	magnetometer: mag3110@e {
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts
@@ -193,8 +193,8 @@
 };

 &clks {
-	clocks = <&clock_ksz8081>;
-	clock-names = "enet_ref_pad";
+	clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clock_ksz8081>;
+	clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
 	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 	assigned-clock-parents = <&clock_ksz8081>;
 };
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts
@@ -66,8 +66,8 @@
 };

 &clks {
-	clocks = <&rmii_clk>;
-	clock-names = "enet_ref_pad";
+	clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&rmii_clk>;
+	clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
 	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 	assigned-clock-parents = <&rmii_clk>;
 };
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts
@@ -119,8 +119,8 @@
 };

 &clks {
-	clocks = <&clock_ksz8081>;
-	clock-names = "enet_ref_pad";
+	clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clock_ksz8081>;
+	clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
 	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 	assigned-clock-parents = <&clock_ksz8081>;
 };
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts
@@ -101,8 +101,8 @@
 };

 &clks {
-	clocks = <&clk50m_phy>;
-	clock-names = "enet_ref_pad";
+	clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
+	clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
 	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 	assigned-clock-parents = <&clk50m_phy>;
 };
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts
@@ -199,8 +199,8 @@
 };

 &clks {
-	clocks = <&clk50m_phy>;
-	clock-names = "enet_ref_pad";
+	clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
+	clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
 	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 	assigned-clock-parents = <&clk50m_phy>;
 };
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts
@@ -294,8 +294,8 @@
 };

 &clks {
-	clocks = <&clk50m_phy>;
-	clock-names = "enet_ref_pad";
+	clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
+	clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
 	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;
 };
--- a/Show More
+++ b/Show More